Apparatus and methods for multi-mode power amplifiers are provided herein. In certain configurations, a wireless device includes a multi-mode power amplifier including a plurality of amplification paths electrically connected in parallel with one another. The plurality of amplification paths includes a first amplification path including an input stage of a first stage type and an output stage of a second stage type, and a second amplification path including an output stage of the second stage type. The first stage type provides non-inverting gain and the second stage type provides inverting gain. The wireless device further includes a transceiver that provides a radio frequency signal to the multi-mode power amplifier, and that operates the multi-mode power amplifier in a selected power mode chosen from a plurality of power modes based on selectively activating one or more of the plurality of amplification paths.

A switched-capacitor power amplifier comprising a plurality of cells and methods for its operation are described. Switched signal lines switch supply to respective capacitors. Switches connect respective signal lines to a first supply and switches connect respective signal lines to a second supply. Pairs of switches on each signal line are switched so that one is switched off whilst the other is switched on. In a full amplitude mode, operation of the switches provides an output having a peak determined by the first supply. A switch signal line is provided between nodes in respective signal lines, a switch being provided in the switch signal line. In a half amplitude mode, switch is switched at the radio frequency in the other direction to that of switches connecting the signal lines to respective ones of the first and second supplies with the other switches being kept open.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

The present invention provides an amplifier circuit, wherein the amplifier circuit includes a DAC, an output stage and a detector. In the operations of the amplifier circuit, the DAC is arranged for performing a digital-to-analog converting operation upon a digital input signal to generate an analog signal, the output stage is arranged for receiving the analog signal to generate an output signal, and the detector is arranged for detecting a characteristic of the input signal, and referring to the characteristic of the input signal to generate at least one control signal to adjust the output stage at a zero-crossing point of the output signal.

A six phase capacitively coupled chopper amplifier. Two phases provide a zeroing phase to zero the feedback capacitors and set the input common mode value. Two phases provide a passive transfer of an input charge from the input capacitors to the zeroed feedback capacitors. The final two phases are chopping and amplification phases. The zeroing phases address the input common mode without the need for biasing resistors. The passive transfer phases resolve the glitching that occurs if the feedback capacitors have to be recharged on each cycle of the chopping clock. Resolving the glitching and the charge time allows the frequency of the amplifier to increase.

Certain aspects of the present disclosure provide a switch architecture for switching between a low power amplifier and a high power amplifier. One example amplification system includes a high power amplifier and a low power amplifier. The amplification system further includes a first switch coupled between the high power amplifier and an output. The amplification system further includes a second switch coupled between the output and a reference potential. The second switch is further coupled between the low power amplifier and the output and configured to selectively couple the low power amplifier to the output. The amplification system further includes a third switch coupled between the low power amplifier and the second switch.

Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.

A power amplifier circuit includes a power amplifier, first and second filters, and first and second output paths. The power amplifier is able to amplify both of a first signal and a second signal. The frequency of the second signal is higher than that of the first signal. The first filter includes a first inductor and attenuates the second signal amplified in the power amplifier. The first inductor serves as a path for the first signal amplified in the power amplifier. The second filter includes a first capacitor and attenuates the first signal amplified in the power amplifier. The first capacitor serves as a path for the second signal amplified in the power amplifier. The first signal outputted from the first filter is supplied to the first output path. The second signal outputted from the second filter is supplied to the second output path.

A wireless communication device includes an amplifier block amplifying a radio frequency (RF) input signal. The amplifier block includes: a first amplification unit and a second amplification unit. The first amplification unit amplifies the RF input signal to generate a first RF amplified signal including a first non-linearity factor and a second RF amplified signal including a second non-linearity factor, and combines the first and second RF signals to generate a third RF amplified signal. The second amplification unit receives and amplifies the third RF amplified signal to output an RF output signal corresponding to the at least one carrier.

Methods and devices for tuning a configurable amplifier of a multi-band RF front-end stage based on a setting of a band switch are described. A lookup table provided with the configurable amplifier is used to map configuration control data of the band switch to configuration control data of the configurable amplifier. The configurable amplifier can be part of a transmit path or a receive path of the multi-band RF front-end stage.