A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

A wide modulation bandwidth radio frequency (RF) circuit is provided. In examples discussed herein, the RF front-end circuit includes a tracker circuit configured to generate a modulated voltage at a wide modulation bandwidth. The modulated voltage can be used by an amplifier circuit(s) for amplifying an RF signal(s). Notably, the tracker circuit may have inherent frequency-dependent impedance that can interact with a load current of the amplifier circuit(s) to cause degradation in the modulated voltage, which can further lead to distortions in an RF offset spectrum. In this regard, a notch circuit is provided and configured to operate at an appropriate notch frequency and a notch bandwidth to filter the modulated voltage in the RF offset spectrum. As a result, it may be possible to reduce the distortions caused by the modulated voltage degradation in the RF offset spectrum, thus helping to improve linearity and efficiency of the amplifier circuit(s).

According to some example embodiments, an apparatus includes a buck-boost converter, a first buck converter connected at an output terminal of the buck-boost converter, a second buck converter connected at the output terminal of the buck-boost converter, a first LA including a first supply voltage input connected to the output terminal of the buck-boost converter, and an output terminal connected to an output terminal of the first buck converter, where the first LA is configured to provide a first modulated supply voltage to a first PA of a first transmitter, and a second LA including a second supply voltage input connected to the output terminal of the buck-boost converter, and an output terminal connected to an output terminal of the second buck converter, where the second LA is configured to provide a second modulated supply voltage to a second PA of a second transmitter.

The disclosed technology includes device, systems, techniques, and methods for amplifying a complex modulated signal with a mixed-signal power amplifier. A mixed-signal power amplifier may include an input network for splitting an input signal to multiple signals with corresponding phase and amplitude offsets, a main power amplification path including at least an analog power amplifier for amplifying a first signal, one or more auxiliary power amplification paths including at least one digitally controlled analog power amplifier in each path for amplifying a second signal, and an output network for combining the two amplified signals. The main power amplification path and the auxiliary power amplification paths can operate together to achieve load modulation to enhance the overall power amplifier efficiency at power back-off mode and the overall power amplifier linearity. The disclosed technology further includes transmission systems incorporating the mixed-signal power amplifier.

A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.

Aspects disclosed in the detailed description include an envelope tracking (ET) amplifier circuit. The ET amplifier circuit includes ET tracker circuitry configured to provide an ET modulated voltage, which tracks an ET modulated target voltage, to an amplifier circuit(s) for amplifying a radio frequency (RF) signal. The ET amplifier circuit also includes fast switcher circuitry that is activated to provide an alternate current (AC) current to the amplifier circuit(s) when the RF signal includes a higher number of resource blocks (RBs). However, the fast switcher circuitry and its associated control circuitry may incur a processing delay that can cause the fast switcher circuitry to lag behind the ET modulated target voltage. As such, the ET amplifier circuit further includes timing adjustment circuitry to help compensate for the processing delay, thus helping to maintain efficiency of the ET tracker circuitry for improved performance of the ET amplifier circuit.

A dual-mode envelope tracking (ET) power management circuit is provided. An ET amplifier(s) in the dual-mode ET power management circuit is capable of supporting normal-power user equipment (NPUE) mode and high-power user equipment (HPUE) mode. In the NPUE mode, the ET amplifier(s) amplifies a radio frequency (RF) signal(s) to an NPUE voltage based on a supply voltage for transmission in an NPUE output power. In the HPUE mode, the ET amplifier(s) amplifies the RF signal(s) to an HPUE voltage higher than the NPUE voltage based on a boosted supply voltage higher than the supply voltage for transmission in an HPUE output power higher than the NPUE output power. The ET amplifier(s) maintains a constant load line between the NPUE mode and the HPUE mode. By maintaining the constant load line, it is possible to maintain efficiency of the ET amplifier(s) in both the NPUE mode and the HPUE mode.

An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.

A system may include a first capacitor, a first switched-mode power supply configured to deliver energy from a power source to the first capacitor at an output load of the first switched-mode power supply, a second capacitor having a capacitance larger than the first capacitor, a second switched-mode power supply configured to deliver energy from the power source or a second power source to the second capacitor and one or more switching elements coupled between the first capacitor and the second capacitor. The system may operate in a plurality of modes, including a first mode in which the first switched-mode power supply transfers energy to the first capacitor and the second capacitor, a second mode in which the second capacitor transfers energy to the first capacitor, and a third mode in which first switched-mode power supply transfers energy to the first capacitor and the second capacitor and the second switched-mode power supply transfers energy to the first capacitor and the second capacitor.

Apparatuses, systems, and methods for implementing a multi-driver architecture are described. The multi-driver architecture may include a first driver and a second driver configured to receive an input voltage. A predriver logic circuit may select one of the first driver and the second driver to convert the input voltage into an output voltage. A controller may be connected to the first driver and the second driver, and a switch may be connected between an output terminal of the first driver and the controller. The controller may be configured to control an internal resistance of the switch. In response to the first driver being selected by the predriver logic circuit, the first driver may output the output voltage at a constant impedance level.