An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a first RF signal input terminal, a first RF signal output terminal, and a transistor. The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value.

Various implementations include circuits, devices and/or methods that provide open loop current limiting power amplifiers and the like. In some implementations, an open loop current clamp includes a trim module to provide a control value and a limiting source having respective input and output terminals. The input terminal is coupled to the trim module to receive the control value. The output terminal coupled to a control terminal of the first transistor to provide a limiting electrical level produced in response to the control value by the limiting source. The limiting electrical level substantially setting a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at an output terminal of the first transistor exerts reduced influence on the current draw.

The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

Techniques for improving electro-static discharge (ESD) performance in integrated circuits (IC's). In an aspect, one or more protective diodes are provided between various nodes of the IC. For example, protective diode(s) may be provided between the drain and gate of an amplifier input transistor, and/or between the drain and ground, etc. In certain exemplary embodiments, the amplifier may be a cascode amplifier. Further aspects for effectively dealing with ESD phenomena are described.

An apparatus is disclosed for implementing a clamping circuit with an interstage matching network or between two amplifier stages to provide power clamping. In example aspects, the apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, an interstage matching network, a power amplifier, and a clamping circuit. The driver amplifier includes a driver amplifier output and is coupled between the input port and the output port. The power amplifier includes a power amplifier input and is coupled between the driver amplifier output and the output port. The interstage matching network is coupled between the driver amplifier output and the power amplifier input. The clamping circuit includes a transistor and a resistor coupled thereto. The clamping circuit is coupled to the interstage matching network via a node that is coupled between the driver amplifier output and the power amplifier input.

An apparatus is disclosed for implementing a Darlington circuit with a driver amplifier to provide power clamping. In example aspects, the apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, a power amplifier, and a Darlington circuit. The driver amplifier includes a driver amplifier output and a transistor, with the driver amplifier coupled between the input port and the output port. The power amplifier includes a power amplifier input, and the power amplifier is coupled between the driver amplifier output and the output port. The Darlington circuit is coupled to the driver amplifier via a node that is coupled between the input port and the power amplifier input.

An apparatus is disclosed for implementing a Darlington circuit with an interstage matching network or between two amplifier stages to provide power clamping. In example aspects, the apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, an interstage matching network, a power amplifier, and a Darlington circuit. The driver amplifier includes a driver amplifier output and is coupled between the input port and the output port. The power amplifier includes a power amplifier input and is coupled between the driver amplifier output and the output port. The interstage matching network is coupled between the driver amplifier output and the power amplifier input. The Darlington circuit is coupled to the interstage matching network via a node that is coupled between the driver amplifier output and the power amplifier input.

A CMOS amplifier including electrostatic discharge (ESD) protection circuits is disclosed. In one embodiment, the CMOS amplifier may include a PMOS transistor, a NMOS transistor, primary protection diodes, and one or more auxiliary protection diodes to limit a voltage difference between terminals of the CMOS amplifier. In some embodiments, the auxiliary protection diodes may limit the voltage difference between an input terminal of the CMOS amplifier and a supply voltage, the input terminal of the CMOS amplifier and ground, and the input terminal and the output terminal of the CMOS amplifier.

A radio-frequency integrated circuit can be protected by a clamp circuit configured to provide electrostatic discharge protection and surge protection for either or both of an amplifier and a related controller. The clamp circuit can include a feedback combination clamp implemented to direct a current associated with either or both of an electrostatic discharge and a surge at a first node to a second node.