An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell having (i) an amplifier configured to receive the electrical current and a reference voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, and (iii) a reset switch coupled in parallel across the feedback capacitor. The apparatus further includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

Provided is an input voltage endurance protection architecture applied to a high-voltage operational amplifier with high input amplitude and high linearity. The input voltage endurance protection architecture includes three parts: a main operational amplifier, an auxiliary operational amplifier and an input stage voltage endurance protection circuit. The main operational amplifier is a high-voltage general-purpose operational amplifier, the auxiliary operational amplifier is a single-stage differential amplifier, and the single-stage differential operational amplifier is connected to a degeneration resistor Rbias. In addition, the auxiliary operational amplifier has a same connection method as the main operational amplifier at a positive input terminal and a negative input terminal, and both the positive input terminal and the negative input terminal are protected by an input stage voltage endurance protection circuit and receive and process input signals simultaneously.

Concurrent electrostatic discharge and surge protection clamps in power amplifiers. In some embodiments, a semiconductor die can include a semiconductor substrate and an integrated circuit implemented on the semiconductor substrate. The integrated circuit can include a power amplifier and a controller. The semiconductor die can further include a clamp circuit implemented on the semiconductor substrate and configured to provide electrostatic discharge protection and surge protection for at least some of the integrated circuit.

A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

An amplifier circuit comprising: a power amplifier; a bias control circuit coupled to the power amplifier and having a voltage sensor configured to sense a bias voltage to the power amplifier, the bias control circuit being configured to determine whether the bias voltage exceeds a threshold voltage; and a protection circuit coupled to the power amplifier, the bias control circuit being further configured to control the protection circuit to apply a clamping status to limit a power output of the power amplifier to a predetermined value in response to the bias control circuit determining that the bias voltage exceeds a threshold voltage.

A power amplifier circuit includes a first amplifier that operates in accordance with a first voltage supplied from a voltage supply source, amplifies a first signal, and outputs an amplification signal, a bias transistor that includes a base or a gate to which a bias control current is supplied and an emitter or a source supplying a bias to the first amplifier through a first resistor element, and a protection circuit that causes part of the bias control current to flow to a ground on the basis of the amplification signal and a second signal based on the first voltage.

A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

A signal output circuit includes an inverting amplifier circuit, a feedback capacitor and a low pass filter. The inverting amplifier circuit includes an input terminal and an output terminal. The inverting amplifier circuit executes an inverting amplification based on an input signal to output a signal to the output terminal at a pull-up state. An output stage of the inverting amplifier circuit is an open collector or an open drain. The feedback capacitor is connected between the input terminal and the output terminal of the inverting amplifier circuit. The low pass filter has an input and an output. The input of the low pass filter is connected to the output terminal of the inverting amplifier. The output of the low pass filter is connected to the feedback capacitor.

Methods and devices for limiting the power level of low noise amplifiers (LNA) implemented in radio frequency (RF) receiver front-ends. The described methods are applicable to bypass, low and high gain modes of the LNA. According to the described methods, the decoder allows the signal to be clamped before or after being attenuated. The benefit of such methods is to improve large signal performances (e.g. IIP3, P1dB) of the RF receiver front-end, while still meeting the clamping requirements, or improve (lower) clamped output power, while still meeting large signal performances (e.g. IIP3, P1dB).

An integrated circuit includes a multiplexer circuit configured to provide an output signal on a conductive line, a programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer, a slew rate adjust circuit connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier, a first switch including a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier, and a low pass filter connected between the first and second terminals of the first switch.