A high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.

The present disclosure includes a photodetector element (11) that converts an optical signal into an electric current signal; a transimpedance amplifier (12a) that converts the electric current signal into a voltage signal; a differential amplifier (12d) that converts the voltage signal into a differential signal, by performing differential amplification of a difference between the voltage signal and a threshold voltage; an LOS detection circuit that detects a no-signal section of the optical signal; and an MCU that repeatedly executes offset cancellation processing, the offset cancellation processing including threshold voltage change processing in which the threshold voltage is changed such that an offset voltage of the differential signal is reduced, the MCU 13 skipping the threshold voltage change processing in the no-signal section.

A circuit may include amplifier circuitry configured to receive a current signal at an amplifier input node, convert the current signal to a voltage signal, and output the voltage signal at an amplifier output node. The circuit may also include overload circuitry configured to receive a replica DC input voltage and a replica DC output voltage. The overload circuitry may be further configured to detect that the current signal exceeds a threshold level based on the replica DC input voltage and the replica DC output voltage. In addition, the overload circuitry may be configured to, in response to and based on detecting that the current signal exceeds the threshold level, direct DC current of the current signal through a DC shunt path and direct AC current of the current signal through an AC shunt path. The AC shunt path may be different from the DC shunt path.

A circuit may include amplifier circuitry configured to receive a current signal at an amplifier input node, convert the current signal to a voltage signal, and output the voltage signal at an amplifier output node. The circuit may also include overload circuitry configured to receive a replica DC input voltage and a replica DC output voltage. The overload circuitry may be further configured to detect that the current signal exceeds a threshold level based on the replica DC input voltage and the replica DC output voltage. In addition, the overload circuitry may be configured to, in response to and based on detecting that the current signal exceeds the threshold level, direct DC current of the current signal through a DC shunt path and direct AC current of the current signal through an AC shunt path. The AC shunt path may be different from the DC shunt path.

A power amplifier circuit includes N (N is an integer equal to or greater than 2) power amplifier circuit cores, which in operation, amplify power of an input signal, N inductors, which in operation, are connected to the N power amplifier circuit cores, and ring-oscillator-type transconductance (gm) generation circuitry, which in operation, generates transconductance (gm) for compensating power loss of the N inductors.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

A high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.

A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice.

A method for making a semiconductor device may include forming active circuitry on a substrate including differential transistor pairs, and forming threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors each includes spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Moreover, each of the channel regions may include a superlattice.

Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror, which may be used for distributed sensing of a remote current in an integrated circuit (IC). One example current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. An input node between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low-voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.