An operational amplifier is disclosed. The operational amplifier activates/couples either a first or a second differential pair of transistors to an input based on the input voltage. The first and second pair of transistors are each biased with a current having a first portion that is constant with temperature and a second portion that is proportional to temperature. By adjusting the ratios of the first and second portions, the transconductance of each differential pair may be made relatively constant with temperature. Each differential pair is coupled to a trim current source that is adjusted to reduce the voltage offset at each output. The resulting voltage offset for the operational amplifier is relatively constant over a range of input voltages and has temperature coefficient unaffected by the trimming process.

Various methods and circuital arrangements for biasing gates of stacked transistors of a cascode amplifier are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback voltage that is based on a sensed voltage at one or more nodes of a replica circuit of the stacked transistors, the amplifier and the replica circuit biased with same gate voltages. According to one aspect, one gate voltage is adjusted based on a comparison of the feedback voltage with a reference voltage, and other gate voltages are derived by offsetting of the one gate voltage with voltages generated by a current flow through a resistive ladder network.

An amplifier includes: a first input transistor connected to a first input, a first output, and a power source or a ground, a second input transistor connected to a second input, a second output, and the power source or the ground; a first replica transistor connected to the first input, a detection node, and the power source or the ground; a second replica transistor connected to the second input, the detection node, and the power source or the ground; and a bias transistor connected to a bias voltage, the detection node, and the power source or the ground.

A signal processor and method. The signal processor includes a signal current path. The signal processor includes a transconductor. The transconductor has an input operable to receive an input voltage of the signal processor. The transconductor also has an output operable to output a current based on the input voltage. The signal processor also includes a processing stage coupled to the output of the transconductor to receive and process the current outputted by the transconductor. The signal processor further includes a current replicator operable to generate a replica current proportional to the current outputted by the transconductor. The signal processor also includes a comparator operable to compare an output of the current replicator with a reference. The signal processor further includes a current limiter operable to limit the current outputted by the transconductor based on the comparison of the output of the current replicator with the reference.

The present disclosure provides for process and temperature compensation in a transimpedance amplifier (TIA) using a dual replica via monitoring an output of a first TIA (transimpedance amplifier) and a second TIA; configuring a first gain level of the first TIA based on a feedback resistance and a reference current applied at an input to the first TIA; configuring a second gain level of the second TIA and a third TIA based on a control voltage; and amplifying a received electrical current to generate an output voltage using the third TIA according to the second gain level. In some embodiments, one or both of the second TIA and the third TIA include a configurable feedback impedance used in compensating for changes in the second gain level due to a temperature of the respective second or third TIA via the configurable feedback impedance of the respective second or third TIA.

Disclosed herein is an apparatus that includes first and second signal lines; a first differential amplifier having an inverting input node receiving an input signal, a non-inverting input node receiving a reference potential, and an output node connected to the first signal line; a second differential amplifier having an inverting input node receiving the reference potential, a non-inverting input node receiving the input signal, and an output node connected to the second signal line; a level shift circuit cross-coupled to the first and second signal lines; a first replica circuit connected to the first signal line; a second replica circuit connected to the second signal line; and a first switch circuit configured to activate one of the level shift circuit, the first replica circuit, and the second replica circuit.

Methods and systems for process and temperature compensation in a transimpedance amplifier using a dual replica and configurable impedances is disclosed and may include a transimpedance amplifier (TIA) circuit comprising a first TIA, a second TIA, a third TIA, and a control loop. The first TIA comprises a fixed feedback resistance and the second and third TIAs each comprise a configurable feedback impedance. The system may comprise a gain stage with inputs coupled to outputs of the first and second TIAs and with an output coupled to the configurable feedback impedance of the second and third TIAs. The circuit may be operable to configure a gain level of the first TIA based on the fixed feedback resistance and a reference current applied at an input to the first TIA, and configure a gain level of the second and third TIAs based on a control voltage generated by the gain stage.

In a Doherty amplifier, outputs of first (main) and second (peak) transistors are connected by a combined impedance inverter and harmonic termination circuit. The harmonic termination circuit incorporates a predetermined part of the impedance inverter, and provides a harmonic load impedance at a targeted harmonic frequency (e.g., the second harmonic). Control of the amplitude and phase of the harmonic load impedance facilitates shaping of the drain current and voltage waveforms to maximize gain and efficiency, while maintaining a good load modulation at a fundamental frequency. Particularly for Group III nitride semiconductors, such as GaN, both harmonic control and output impedance matching circuits may be eliminated from the outputs of each transistor. The combined impedance inverter and harmonic termination circuit reduces the amplifier circuit footprint, for high integration and low power consumption.

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

A buffer circuit may include: an amplifying circuit configured to change, based on a first input signal and a second input signal, voltage levels of a first output node and a second output node in a range between a first power voltage and a second power voltage; a latch circuit configured to latch the voltage levels of the first output node and the second output node; a first variable load configured to adjust, based on a reset signal, an amount of current provided by a first power voltage terminal at the first power voltage to the first output node; a second variable load configured to adjust, based on the reset signal, an amount of current provided by the first power voltage terminal to the second output node; and a reset circuit configured to drive the first output node to the second power voltage based on the reset signal.