A circuit includes a transformer having a primary coil coupled to a first power amplifier (PA) and a second PA, and a secondary coil. The secondary coil supplies a current to an antenna based on a first direction of a first phase of a first amplified constant-envelope signal in the primary coil with respect to a second phase of a second amplified constant-envelope signal in the primary coil. The circuit further includes load impedance coupled between a median point of the primary coil and ground. The load impedance dissipates the current based on a second direction of the first phase of the first amplified constant-envelope signal in the primary coil with respect to the second phase of the second amplified constant-envelope signal in the primary coil, which results in improved power efficiency.

A push-pull power amplifier (PA) includes a pair of P-type transistors, a pair of N-type transistors, and a splitter, wherein source terminals of the pair of P-type transistors are coupled to a first reference voltage, source terminals of the pair of N-type transistors are coupled to a second reference voltage, and drain terminals of the pair of P-type transistors and drain terminals of the pair of N-type transistors are coupled to an output port of the push-pull PA. The splitter is arranged to receive a common-mode input pair, and provide two differential output pairs to the pair of P-type transistors and the pair of N-type transistors, wherein one of the two differential output pairs is provided to gate terminals of the pair of P-type transistors, and the other of the two differential output pairs is provided to gate terminals of the pair of N-type transistors.

A signal amplifier circuit having high power supply rejection ratio includes: a pre-amplifier which generates a driving signal at a driving control node; and a driving circuit which converts an input power to an output power. The driving circuit includes: a driving transistor, having a first terminal coupled to the input power and a second terminal coupled to the output power; and a power rejection circuit which includes a noise selection circuit. When the driving transistor operates in its linear region, the power rejection circuit senses an AC component of a power noise of the input power to generate an operation noise signal. The power rejection circuit generates the power rejection signal in AC form according to the operation noise signal to reject the power noise so as to increase the power supply rejection ratio.

An amplifier system having first and second interleaved half bridge stages and a coupled inductor. The coupled inductor has a primary winding and a secondary winding, a first end of the primary winding is coupled to the first half bridge stage at a first node, a second end of the primary winding is coupled to the load, a first end of the secondary winding is coupled to the load, a second end of the secondary winding is coupled to the second half bridge stage at a second node. An inductor circuit is coupled between the first and second half bridge stages and a first end of a load circuit.

A signal amplifier includes one or more driver stage amplifiers and a power stage amplifier. The one or more driver stage amplifiers are connected in series. The one or more driver stage amplifiers and the power stage amplifier are connected to the same power supply, such that each of the at least one driver stage amplifier forms a loop with the power stage amplifier. The signal amplifier can further include a wave trap unit configured to block an oscillation frequency in the loop. One terminal of the wave trap unit is connected to the loop. The other terminal of the wave trap unit is grounded.

Neuromodulation systems in accordance with embodiments of the invention can use a feed-forward common-mode cancellation (CMC) path to attenuate common-mode (CM) artifacts appearing at a voltage input, thus allowing for the simultaneous recording of neural data and stimulation of neurons. In several embodiments of the invention, the feed-forward CMC path is utilized to attenuate the common-mode swings at V.sub.in,CM, which can restore the linear operation of the front-end for differential signals. In several embodiments, the neuromodulation system may utilize an anti-alias filter (AAF) that includes a duty-cycles resistor (DCR) switching at a first frequency f.sub.1, followed by a DCR switching at a second frequency f.sub.2. The AAF allows for a significantly reduced second frequency f.sub.2 that enables the multi-rate DCR to increase the maximum realizable resistance, which is dependent upon the frequency ratio f.sub.1/f.sub.2.

According to an exemplary embodiment, a capacitively coupled continuous-time delta-sigma modulator includes an instrumentation amplifier amplifying an input voltage to an output voltage of a predetermined magnitude, a delta-sigma modulator outputting a bit signal quantized depending on a sampling frequency based on the output voltage and to convert the bit signal into a digital-to-analog conversion voltage, and a ripple reduction loop unit generating a demodulation voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency to feed the demodulation voltage back to the instrumentation amplifier. The RRL operating frequency is equal to the sampling frequency.

A circuit includes a transformer having a primary coil coupled to a first power amplifier (PA) and a second PA, and a secondary coil. The secondary coil supplies a current to an antenna based on a first direction of a first phase of a first amplified constant-envelope signal in the primary coil with respect to a second phase of a second amplified constant-envelope signal in the primary coil. The circuit further includes load impedance coupled between a median point of the primary coil and ground. The load impedance dissipates the current based on a second direction of the first phase of the first amplified constant-envelope signal in the primary coil with respect to the second phase of the second amplified constant-envelope signal in the primary coil, which results in improved power efficiency.

A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.

The outphasing power combiner circuit includes a transformer having a primary coil coupled to a first power amplifier (PA) and a second PA, and a secondary coil. The secondary coil supplies a current to an antenna based on a first direction of a first phase of a first amplified constant-envelope signal in the primary coil with respect to a second phase of a second amplified constant-envelope signal in the primary coil. The outphasing power combiner circuit further includes load impedance coupled between a median point of the primary coil and ground. The load impedance dissipates the current based on a second direction of the first phase of the first amplified constant-envelope signal in the primary coil with respect to the second phase of the second amplified constant-envelope signal in the primary coil, which results in improved power efficiency.