An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.

Processes and systems for producing glass fibers having regions devoid of glass using submerged combustion melters, including feeding a vitrifiable feed material into a feed inlet of a melting zone of a melter vessel, and heating the vitrifiable material with at least one burner directing combustion products of an oxidant and a first fuel into the melting zone under a level of the molten material in the zone. One or more of the burners is configured to impart heat and turbulence to the molten material, producing a turbulent molten material comprising a plurality of bubbles suspended in the molten material, the bubbles comprising at least some of the combustion products, and optionally other gas species introduced by the burners. The molten material and bubbles are drawn through a bushing fluidly connected to a forehearth to produce a glass fiber comprising a plurality of interior regions substantially devoid of glass.

An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source input stage and a common gate output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.

A high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.