Low-noise amplifier having programmable-phase gain stage. In some embodiments, a radio-frequency amplifier can include an input node, an output node, and a programmable-phase gain stage implemented between the input node and the output node. The programmable-phase gain stage can be configured to operate in one of a plurality of gain settings, and to provide a desired phase for a signal at each of the plurality of gain settings.

A high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.

A linear low noise amplifier is disclosed. In at least one exemplary embodiment, the linear low noise amplifier may include a first metal oxide semiconductor field effect transistor (MOSFET) configured to operate in a triode mode coupled to a second MOSFET configured to operate in a saturation mode. Linearity of the low noise amplifier may be determined, at least in part, by a transconductance associated with the second MOSFET and a channel resistance associated the first MOSFET.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Methods and devices to mitigate the detrimental effects of highly capacitive output routes of multiple gain low noise amplifiers on the overall performance of the circuit are disclosed. The disclosed methods and devices implement the same inductive element across the output load in both the low gain and high gain operational modes. Furthermore, such devices implement switches to control the selection of different signal paths for the high gain and low gain mode. The implemented switches are also used to selectively adjust the isolation of the output stage of the LNA.

Techniques for providing low-cost and effective jammer rejection for an amplifier is disclosed. The amplifier includes an input node and an output node, a first transistor and a second transistor, a load circuitry, an inductor, and a capacitor. A first terminal of the first transistor is coupled to a ground. A second terminal of the first transistor is coupled to a first terminal of the second transistor. A second terminal of the second transistor is coupled to the output node. The load circuitry is coupled between a power supply and the second terminal of the second transistor. A first terminal of the inductor is coupled to the ground through a first switch. A first terminal of the capacitor is coupled to the first terminal of the second transistor and a second terminal of the capacitor is coupled to a second terminal of the inductor.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a common source input transistor, e.g., input field effect transistor (FET), and the second configured in a common gate configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

A radio frequency low noise amplifier circuit with a receive signal input, a receive signal output, and a voltage source include a low noise amplifier and a coupled inductor circuit with a primary inductive chain connected to the output of the low noise amplifier and to the voltage source. The coupled inductor circuit further includes a secondary inductive chain with a first inductor electromagnetically coupled to the primary inductive chain, and a second inductor in series with the first inductor and magnetically coupled to the primary inductive chain. The second inductor is connected to a feedback node of the low noise amplifier. There is an output matching network connected to the first inductor of the secondary inductive chain and to the receive signal output.