An amplifier circuit includes: a transistor provided between an input terminal and an output terminal and having a gate connected to the input terminal, a source connected to a ground, and a drain connected to the output terminal; an inductor connected between the source and the ground; an inductor connected between the gate and the input terminal, and switches connected to at least one of the inductors and configured to change a mutual inductance of the inductors.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

An amplifier circuit (1) includes a FET (10) having a source terminal (S1), a drain terminal (D1), and a gate terminal (G1), a FET (20) having a source terminal (S2), a drain terminal (D2), and a gate terminal (G2) and coupled in parallel with the FET (10), a FET (30) having a source terminal (S3) coupled to the drain terminals (D1 and D2), a drain terminal (D3), and a gate terminal (G3) and cascoded with the FETs (10 and 20), and feedback circuits (21 and 22) configured to feed back to the gate terminal (G2) a high frequency signal outputted from the source terminal (S2) or the drain terminal (D2).

This disclosure describes amplifiers that include impedance circuits that are configured to adapt to various contexts. For example, a variable-gain amplifier can include a gain circuit configured to amplify a signal and to operate in a plurality of gain modes, and an impedance circuit coupled to the gain circuit. The impedance circuit can include an inductor and a switching-capacitive arm coupled in parallel to the inductor. The impedance circuit can be configured to operate based at least in part on a gain mode from among the plurality of gain modes.

This disclosure relates to variable-gain amplifiers that include degeneration circuits configured to adapt to a gain mode that is currently being implemented. For example, a variable-gain amplifier can operate in a plurality of gain modes to amplify a signal with different levels of amplification. The variable-gain amplifier can include a gain circuit configured to amplify a signal and a degeneration circuit coupled to the gain circuit. The degeneration circuit can include an inductor and a switching-capacitive arm coupled in parallel to the inductor. The degeneration circuit can operate based on a current gain mode to change an inductance for the variable-gain amplifier.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor; a second transistor; and a third transistor, wherein: the first, second and third transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. There is also disclosed a receiver incorporating the amplifier and methods of operating the amplifier.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.