Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

Radio frequency (RF) amplifier circuitry includes an input node, an output node, an amplifier, and bootstrap circuitry. The amplifier includes a control node coupled to the input node, a first amplifier node coupled to the output node, and a second amplifier node coupled to a fixed potential. The amplifier is configured to receive an input signal having a first frequency at the control node and change an impedance between the first amplifier node and the second amplifier node based on the input signal. The bootstrap circuitry is coupled between the control node and the second amplifier node. The bootstrap circuitry is configured to provide a low impedance path between the control node and the second amplifier node for signals having a second frequency that is equal to about twice the first frequency and provide a high impedance path for signals having a frequency outside the second frequency.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

Radio frequency (RF) amplifier circuitry includes an input node, an output node, an amplifier, and bootstrap circuitry. The amplifier includes a control node coupled to the input node, a first amplifier node coupled to the output node, and a second amplifier node coupled to a fixed potential. The amplifier is configured to receive an input signal having a first frequency at the control node and change an impedance between the first amplifier node and the second amplifier node based on the input signal. The bootstrap circuitry is coupled between the control node and the second amplifier node. The bootstrap circuitry is configured to provide a low impedance path between the control node and the second amplifier node for signals having a second frequency that is equal to about twice the first frequency and provide a high impedance path for signals having a frequency outside the second frequency.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.

A multi-stage device includes multiple stages such as a first stage and a second stage. During operation, the first stage receives an input signal and outputs an intermediate signal based on the input signal. The second stage is coupled to the first stage to receive the intermediate signal and produce an output signal. According to one configuration, the second stage includes: i) a transistor, and ii) a circuit path between the first stage and the transistor. The transistor component is controlled to derive the output signal from the intermediate signal inputted to the circuit path.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g m of the input stage of the amplifier, thus improving the noise figure of the amplifier.