The operational amplifier disclosed includes an input stage configured to receive power from a floating supply in a low voltage range that can float according to the common mode voltage at the input. The floating supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage includes a first gain stage including field effect transistors and a second gain stage using bipolar transistors. The gain stages can be implemented differently to accommodate different applications and fabrication capabilities.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An ultrasound probe buffer is provided. The ultrasound probe buffer may include a high impedance amplifier having a common-source core stage with series-series local feedback. The high impedance amplifier may include a first MOSFET and a second MOSFET, wherein a source terminal of the first MOSFET is coupled to a source terminal of the second MOSFET.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

A semiconductor device includes a low power fast differential transconductor, which provides an output current as a function of a difference between a reference potential input and a feedback potential input. The transconductance increases as an absolute value of the difference between the reference potential and the feedback potential increases. The transconductor includes a reference input stage to receive the reference potential and a reference load coupled in series with the reference input stage. The transconductor includes a feedback input stage to receive the feedback potential and a feedback load coupled in series with the feedback input stage. The transconductor further includes a current limiting component that is configured to control a total current through the reference input stage and the feedback input stage. The transconductor includes a negative feedback path from the reference load to the current limiting component, that compensates for changes in the total current due to differences between the reference potential and the feedback potential.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

In accordance with an embodiment, a circuit includes: a replica input transistor, a first replica cascode transistor, an active current source, and an active cascode biasing circuit. The active current source is configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a control node of the replica input transistor; and an active cascode biasing circuit including a first output coupled to the control node of the first replica cascode transistor, and the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the control node of the first replica cascode transistor.

An RF amplifier is described including an input, an output, a parallel arrangement of a first branch and at least one further branch, each branch comprising a bipolar transistor in a degenerative emitter configuration having a base coupled to the input, a collector coupled to a common collector node, and an emitter degeneration impedance arranged between the emitter and a common rail. The common collector node is coupled to the output, the base of the first branch bipolar transistor is biased at a first bias voltage and the base of the at least one further branch bipolar transistor is biased at a bias voltage offset from the first bias voltage. In operation of the RF amplifier a IM3 distortion current output by the first branch bipolar transistor is in antiphase to a IM3 distortion current output by the at least one further branch bipolar transistor.

Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.