A power amplifier circuit includes a first amplifier that amplifies a first signal, and a second amplifier arranged subsequent to the first amplifier. The second amplifier amplifies a second signal that is based on an output signal of the first amplifier. The first amplifier performs class inverse-F operation, and the second amplifier performs class F operation.

A multi-voltage generation circuit and related envelope tracking (ET) amplifier apparatus is provided. In one aspect, a multi-voltage generation circuit is configured to generate a number of ET target voltages based on an analog voltage signal. In another aspect, a multi-amplifier ET circuit can be configured to include a number of amplifier circuits for amplifying concurrently a radio frequency (RF) signal based on a number of ET voltages. The multi-amplifier ET circuit also includes a number of driver circuits configured to generate the ET voltages base on a number of ET target voltages. In this regard, the multi-voltage generation circuit can be provided in the multi-amplifier ET circuit to generate the ET target voltages based on the analog voltage signal that corresponds to the RF signal. In examples discussed herein, the driver circuits are co-located with the amplifier circuits to help improve efficiency and maintain linearity in the amplifier circuits.

Apparatuses and methods for adjusting a power capability of a system is described. In an example, a system can include an antenna array and a beamformer connected to the antenna array. The beamformer can include a communication channel. The system can further include a first power converter that can be configured to convert a supply voltage to a first regulated voltage. The first power converter can apply the first regulated voltage to the beamformer. The system can further include a second power converter that can be configured to convert the supply voltage to a second regulated voltage different from the first regulated voltage. The second power converter can apply the second regulated voltage to a power amplifier in the communication channel to adjust a maximum power capability of the power amplifier.

An amplifier transistor operates in two operation modes having different characteristics. A first bias circuit including a first bias supply transistor supplies an output current of the first bias supply transistor to the amplifier transistor as a bias current. A second bias circuit including a second bias supply transistor supplies a portion of an output current of the second bias supply transistor to the amplifier transistor as a bias current. At least one of the first bias circuit and the second bias circuit is selected and operates in accordance with an operation mode of the amplifier transistor by using a bias control signal input to a bias control terminal. The second bias circuit includes a current path along which a portion of the output current of the second bias supply transistor is returned to the second bias circuit.

A receiver circuit may be provided. The receiver circuit may include a first duty cycle adjuster configured to correct a duty cycle of a first output signal pair. The receiver circuit may include a second duty cycle adjuster configured to correct a duty cycle of a second output signal pair, based on the first output signal pair, after the first duty cycle adjuster performs a correction on the duty cycle of the first output signal pair.

A radio frequency power amplifier (RF PA) apparatus includes a first RF PA, a second RF PA, and a controller. The first RF PA is configured to deliver RF power to a load over a first range of RF power levels. The second RF PA is configured to deliver RF power to the load over a second range of RF power levels greater than the first range of RF power levels. The controller controls whether the first RF PA is delivering RF power to the load or the second RF PA is delivering RF power to the load, and is further configured to coordinate and control handoffs between the first and second RF PAs by varying magnitudes of input RF voltages applied to the RF input ports of the first and second RF PAs or by varying magnitudes of input bias voltages applied to the RF input ports of the first and second RF PAs.

Apparatus and methods for power amplifiers with an injection-locked oscillator driver stage are provided herein. In certain configurations, a multi-mode power amplifier includes a driver stage implemented using an injection-locked oscillator and an output stage having an adjustable supply voltage that changes based on a mode of the multi-mode power amplifier. By implementing the multi-mode power amplifier in this manner, the multi-mode power amplifier exhibits excellent efficiency, including when the voltage level of the adjustable supply voltage is relatively low.

A high-frequency front-end circuit includes a plurality of power amplifiers. Power supply inductors and matching inductors for the power amplifiers are formed of conductors disposed on a substrate. The power supply inductors and the matching inductors are disposed on or in different layers. When the substrate is seen in a plan view, at least a portion of the first power supply inductor and at least a portion of the second matching inductor overlap each other with an insulating layer interposed therebetween.

A power amplifier has improved power added efficiency at high output power. The power amplifier includes: a first transistor for amplifying an input signal input to the base thereof and outputting the amplified signal from the collector thereof; a second transistor with power-supply voltage applied to the collector thereof to supply bias voltage or bias current from the emitter thereof to the base of the first transistor; a third transistor whose collector is connected to the collector of the first transistor to amplify the input signal input to the base thereof and output the amplified signal from a collector thereof; a fourth transistor whose base and collector are connected to supply bias from the emitter thereof to the base of the third transistor; and a first resistor with bias control voltage applied to one end thereof and the other end connected to the bases of the second and fourth transistors.

An apparatus includes a first predistorter configured to calculate a first predistortion parameter and configured to distort an input signal using the first predistortion parameter to output a first distortion signal, a second predistorter configured to calculate a second predistortion parameter and configured to distort the first distortion signal using the second predistortion parameter to output a second distortion signal, a power supply configured to receive the first distortion signal to generate a first envelope signal, and configured to limit a bandwidth of the first envelope signal to obtain a second envelope signal to supply a source voltage, and a power amplifier configured to receive the source voltage and to output an output signal obtained by amplifying the second distortion signal.