Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.

Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.

Current-mode control for radio-frequency (RF) power amplifiers. In some embodiments, an RF power amplifier control circuit can include a sensor configured to measure a base current of a power amplifier and generate a sensed current. The control circuit can further include a sensing node configured to receive a reference current and perform a current-mode operation with the sensed current to yield an error current. The control circuit can further include a control loop configured to generate a control signal based on the error current to adjust an operating parameter of the power amplifier.

Pulse shaping biasing circuitry includes square wave generator circuitry, first inverse ramp signal generator circuitry, and second inverse ramp signal generator circuitry. The square wave generator circuitry is coupled between an input node and signal summation circuitry, and is configured to generate a square wave signal. The first inverse ramp signal generator circuitry is coupled in parallel with the square wave generator circuitry and configured to generate a first inverted ramp signal. The second inverse ramp signal generator circuitry is coupled in parallel with the square wave generator circuitry and the first inverse ramp signal generator circuitry and configured to generate a second inverted ramp signal. The square wave signal, the first inverted ramp signal, and the second inverted ramp signal are combined by the signal summation circuitry to provide a pulse shaping bias signal for a radio frequency (RF) power amplifier.

Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.

A pseudo resistor circuit and a charge amplifier include a first field effect transistor; a second field effect transistor having electrical characteristics matched with electrical characteristics of the first field effect transistor; and a voltage dividing circuit with terminal of a reference resistor electrically connected to a source terminal of the second field effect transistor. Further, a first operational amplifier with an output terminal is connected to a gate terminal of the first field effect transistor and a gate terminal of the second field effect transistor and in which midpoint voltage of the voltage dividing circuit is input into either an inverting or non-inverting input terminal and reference voltage is input into the other of the inverting and non-inverting input terminal. Furthermore, a second operational amplifier supplies voltage resulting from inversion and amplification of drain voltage of the first field effect transistor into the other terminal of the resistor.

A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

A current voltage conversion circuit includes first to fourth signal amplifiers; and first and second resistive passive elements, an input terminal of the first signal amplifier being connected to a terminal for inputting a current signal, one and the other terminals of the first resistive passive element being connected to output and input terminals of the first signal amplifier, respectively, an input terminal of the second signal amplifier being connected to a first connection point, input and output terminals of the third signal amplifier being connected to an output terminal of the second signal amplifier and the first connection point, respectively, an input terminal of the fourth signal amplifier being connected to a second connection point, and one and the other terminals of the second resistive passive element being connected to an output terminal of the fourth signal amplifier and the second connection point.

Reference circuits for biasing radio frequency electronics are provided herein. In certain implementations, a gallium arsenide die includes a power amplifier configured to provide amplification to a signal, a reference voltage circuit including an output terminal that provides a reference voltage, and a mirror circuit configured to bias the power amplifier based on the reference voltage. The reference voltage circuit includes a bipolar transistor, a field effect transistor, and a circuit portion that generates a voltage that is proportional to absolute temperature. The reference voltage circuit generates the reference voltage based on a sum of a base-to-emitter voltage of the bipolar transistor, a turn-on voltage of the field effect transistor, and the voltage that is proportional to absolute temperature.

A circuit for generation of a reference voltage for an electronic system, which circuit comprises at least one digital buffer (U21, U31, U32, U41, U51), a low pass filter (R21, C21; R31, C31; R41, C41; R51, C51) and an operational amplifier (OA21, OA31, OA41, OA51)), which circuit is adapted to revive an input in the form of a bandgap reference voltage into the digital buffer, which digital buffer is adapted to receive a digital input from a Pulse Width Modulated (PWM) signal, which digital buffer is adapted to generate an output signal adapted to be fed to the low pass filter, which output signal after filtration is adapted to be fed to a positive input terminal of the operational amplifier, which operational amplifier comprises a feedback circuit, which feedback circuit comprises at least one capacitor (C22, C32, C44, C54) adapted to be connected from an output terminal of the operational amplifier towards a negative input terminal of the operational amplifier so as to form an integrator, wherein the feedback circuit further comprises at least one chopped signal path (R22, S21; R33, R34, S32; R33, R35, C35, S31), which chopped signal is adapted to be modulated by the output signal of the digital buffer.