A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

A power amplifier circuit includes a first transistor amplifying a first signal; a second transistor amplifying a second signal; a bias circuit supplying a bias current or voltage to a base or gate of the second transistor; and an attenuator attenuating the first or second signal in accordance with a control voltage supplied from the bias circuit. The attenuator includes a first diode to which the control voltage is supplied, a third transistor including a collector connected to a supply path of the first or second signal, an emitter connected to a ground, and a base to which the control voltage is supplied from the first diode, and a capacitor connected in parallel with the first diode. The control voltage decreases as a second signal power level increases. The third transistor allows part of the first or second signal to pass to the emitter in accordance with the control voltage.

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

An amplifier circuit with in-band gain degradation compensation is shown. The amplifier circuit has an input-stage amplifier, at least one intermediate-stage amplifier, and an output-stage amplifier cascaded between an input port and an output port of the amplifier circuit. A compensation capacitor is coupled between the output port of the amplifier circuit and an output port of the input-stage amplifier. A high-order damping circuit is coupled to an output port of the intermediate-stage amplifier.

An amplification circuit includes: an amplifier including a transistor that is connected between an input terminal and an output terminal; an input matching network that is connected between the input terminal and an input side of the amplifier and converts an impedance from a low impedance to a high impedance; a limiter circuit that is connected between a node between the input matching network and the input side of the amplifier, and ground and includes two diodes connected in opposite directions to each other; and a capacitor that is connected in series with the limiter circuit between the node and ground.

An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor; a second transistor; and a third transistor, wherein: the first, second and third transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. There is also disclosed a receiver incorporating the amplifier and methods of operating the amplifier.

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

A power amplifier module that includes a power amplifier and a controller is presented herein. The power amplifier module may include a set of transistor stages and a plurality of bias circuits. At least one transistor stage from the set of transistor stages may be in electrical communication with a first bias circuit and a second bias circuit from the plurality of bias circuits. The first bias circuit can be configured to apply a first bias voltage to the at least one transistor stage and the second bias circuit can be configured to apply a second bias voltage to the at least one transistor stage. The controller may be configured to activate one of the first bias circuit and the second bias circuit.

An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.