H03F2200/66

METHOD AND DEVICE FOR DIGITAL COMPENSATION OF DYNAMIC DISTORTION IN HIGH-SPEED TRANSMITTERS

A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.

High dynamic range transimpedance amplifier

Aspects of this disclosure relate to a receiver for a light detection and ranging system. The receiver includes a transimpedance amplifier that is operable in a linear mode for a range of power of light received by the receiver. The receiver can provide information about amplitude of the light outside of the range of power of the light for which the transimpedance amplifier operates in the linear mode. This information can be useful, for example, in identifying an object from which light received by the receiver was reflected.

Avoiding clipping in audio power delivery by predicting available power supply energy
10998867 · 2021-05-04 · ·

A power output circuit supplies an audio power output signal that is adjusted to prevent clipping when needed based on an estimate of available energy from the power supply supplying the power output circuit. The power output circuit may be an audio power output circuit that generates an audio power output signal from samples of an audio program that are stored in a buffer. A processing block determines an energy requirement for producing the audio power output signal from the audio program and adjusts an amplitude of the audio power output signal in conformity with the determined energy requirement and an available energy determined for the power supply so that the audio power output signal is reproduced without clipping of the audio power output signal.

Method and device for digital compensation of dynamic distortion in high-speed transmitters

A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.

AMPLIFIER WITH AN AT LEAST SECOND ORDER FILTER IN THE CONTROL LOOP
20200382084 · 2020-12-03 ·

A Class D amplifier having an integrating primary amplifier with an internal feedback, the amplifier further comprising a feedback loop with a filter of at least second order.

AVOIDING CLIPPING IN AUDIO POWER DELIVERY BY PREDICTING AVAILABLE POWER SUPPLY ENERGY
20200382078 · 2020-12-03 ·

A power output circuit supplies an audio power output signal that is adjusted to prevent clipping when needed based on an estimate of available energy from the power supply supplying the power output circuit. The power output circuit may be an audio power output circuit that generates an audio power output signal from samples of an audio program that are stored in a buffer. A processing block determines an energy requirement for producing the audio power output signal from the audio program and adjusts an amplitude of the audio power output signal in conformity with the determined energy requirement and an available energy determined for the power supply so that the audio power output signal is reproduced without clipping of the audio power output signal.

High dynamic range analog front-end receiver for long range LIDAR

A system and method for operating a high dynamic range analog front-end receiver for long range LIDAR with a transimpedance amplifier (TIA) include a clipping circuit to prevent saturation of the TIA. The output of the clipping circuit is connected via a diode or transistor to the input of the TIA and regulated such that the input voltage of the TIA remains close to or is only slightly above the saturation threshold voltage of the TIA. The regulation of the input voltage of the TIA can be improved by connecting a limiting resistor in series with the diode or transistor. A second clipping circuit capable of dissipating higher input currents and thus higher voltages may be connected in parallel with the first clipping circuit. A resistive element may be placed between the first and second clipping circuits to further limit the input current to the TIA.

Signal processing device and transceiver
10797717 · 2020-10-06 · ·

A signal processing device includes an A-D converter and a controller. The A-D converter converts an analog signal to a digital signal in which portions where the amplitude exceeds a predetermined range are clipped. A counter of the controller calculates, for the digital signal, a number of clipped samples for each predetermined number of period samples. A frequency converter performs frequency conversion of the digital signal. An LPF removes high frequency components of the digital signal. A rate converter converts a sampling rate of the A-D converter. A digital amplifier amplifies and outputs the digital signal. An amplification factor adjuster multiplies a preset amplification factor of the digital amplifier by an amplification factor adjustment coefficient based on a ratio of the number of regular samples to the number of period samples, to adjust the amplification factor.

Crest factor reduction in power amplifier circuits

Techniques are described for crest factor reduction in power amplifier circuits. For example, crest factor reduction can keep the peak signal level of a signal for transmission to below a peak threshold level associated with a power amplifier in the transmission path. The signal is received by the crest factor reduction system and clipped in accordance with the peak threshold level. Edge smoothing is then applied to the clipped signal to reduce out-of-band emissions. The edge smoothing is implemented by a moving average filter, such as a time-domain box filter. In some embodiments, a maximum operation or minimum operation is used to prevent signal peak regrowth after the filtering. Some embodiments also include various iteration loops to further improve crest factor reduction.

PWM CLIPPING DETECTOR CIRCUIT, CORRESPONDING ELECTRONIC SYSTEM AND METHOD
20200280287 · 2020-09-03 ·

A clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to monitor a time period elapsing since a last occurrence of an edge in a PWM signal, assert a first signal when the time period elapses, and de-assert the first signal and reset the time period as a result of an edge occurring in the PWM signal. The counter circuit is configured to determine a number of pulses in the PWM signal since the last de-assertion of the first signal, and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to generate a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal.