An integrated circuit, comprising an amplifier comprising a pair of inputs configured to receive a differential signal, a first resistor, a second resistor, wherein the first resistor and the second resistor are coupled in series with each other and coupled to a first input of the pair of inputs, a third resistor, a fourth resistor, wherein the third resistor and the fourth resistor are coupled in series with each other and coupled to a second input of the pair of inputs, and a first capacitor comprising a first end coupled to a first point between the first resistor and the second resistor, and a second end coupled to a second point between the third resistor and the fourth resistor, a second capacitor disposed between the first input and an output of the amplifier; and a third capacitor disposed between the second input and the output.

A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.

Techniques are described for crest factor reduction in power amplifier circuits. For example, crest factor reduction can keep the peak signal level of a signal for transmission to below a peak threshold level associated with a power amplifier in the transmission path. The signal is received by the crest factor reduction system and clipped in accordance with the peak threshold level. Edge smoothing is then applied to the clipped signal to reduce out-of-band emissions. The edge smoothing is implemented by a moving average filter, such as a time-domain box filter. In some embodiments, a maximum operation or minimum operation is used to prevent signal peak regrowth after the filtering. Some embodiments also include various iteration loops to further improve crest factor reduction.

A signal processing device includes an A-D converter and a controller. The A-D converter converts an analog signal to a digital signal in which portions where the amplitude exceeds a predetermined range are clipped. A counter of the controller calculates, for the digital signal, a number of clipped samples for each predetermined number of period samples. A frequency converter performs frequency conversion of the digital signal. An LPF removes high frequency components of the digital signal. A rate converter converts a sampling rate of the A-D converter. A digital amplifier amplifies and outputs the digital signal. An amplification factor adjuster multiplies a preset amplification factor of the digital amplifier by an amplification factor adjustment coefficient based on a ratio of the number of regular samples to the number of period samples, to adjust the amplification factor.

A voltage controlled amplifier with an amplitude limiting circuit, such as a clip limiter, that is separate from the signal path on which the input signal is received by a power amplifier can reduce both noise and power expenditure of the voltage controlled amplifier. The amplitude limiting circuit can include a transistor network that is controlled by a pair of utility operational amplifiers. These utility amplifiers may use less current than the audio amplifier of the voltage controlled amplifier. Further, the transistor network can be deactivated when a signal supplied to the voltage controlled amplifier is below a clipping or other voltage limiting threshold.

An apparatus for controlling the gain and phase of an input signal input to a power amplifier comprises a gain control loop configured to control the gain of the input signal based on power levels of the input signal and an amplified signal output by the power amplifier, to obtain a predetermined gain of the amplified signal, and a phase control loop configured to obtain an error signal related to a phase difference between a first signal derived from the input and a second signal derived from the amplified signal, and control the phase based on the error signal, to obtain a predetermined phase of the amplified signal. The phase control loop delays the first signal such that the delayed first signal and the second signal used to obtain the error signal correspond to the same part of the input signal. The apparatus may be included in a satellite.

A trans-impedance amplifier (TIA) includes a first circuit, a second circuit, and a third circuit. Both the first circuit and the second circuit are coupled to a current source, an operational amplifier, and the third circuit. The first circuit is configured to receive a first current, provide a third voltage to the third circuit, perform shape filtering on the first current, and convert the shape filtered first current to a first voltage for output. The second circuit is configured to receive a second current, provide a fourth voltage to the third circuit, perform shape filtering on the second current, and convert the shape filtered second current to a second voltage for output. The third circuit is configured to cooperate with the first circuit and the second circuit in performing shape filtering. The operational amplifier is configured to provide a small-signal virtual ground point to the first circuit.

A crest factor reduction (CRF) circuit may include a scaler configured to receive the input signal and generate a scaled input signal. A clipping circuit may be configured to receive the input signal and generate a clipped input signal. A negator circuit may be configured to receive the clipped input signal and generate a negated clipped input signal. A first summer may be configured to sum the scaled input signal and the negated clipped input signal to generate a summed signal. A first digital filter may be configured to receive the summed signal and provide a first digital filter output. A second digital filter may be configured to receive the clipped input signal and provide a second digital filter output. A multiplexer may be configured to receive the first digital filter output and the second digital filter output and generate an output signal.

An anti-clipping circuit for car audio systems. The circuit reduces the input voltage from a signal source to an analog-to-digital converter by using a divider or by scaling the output of the pre-amplifier to less than the saturation voltage of the ADC. A digital signal processor (DSP) with a limiter algorithm ensures that the signal never exceeds a selected threshold. Then, a multiplying block in the DSP restores the signal to the original voltage level. The anti-clipping circuit protects the speakers from high total harmonic distortion (THD) levels and from distortion during engine start-up. It can also be used for thermal power rollback.

A distortion device includes a transconductance stage, a current amplifier stage electrically coupled to the transconductance stage, and a transformer portion electrically coupled to the current amplifier stage. The transconductance stage includes a first capacitor to provide a ground to a resistor, and voltage across the resistor develops a current through a second capacitor to the current amplifier stage. The current amplifier stage includes a positive half cycle and a negative half cycle. The positive half cycle and the negative half cycle amplify the current from the transconductance stage and supply the amplified current to a primary winding of a transformer in the transformer portion, and the output of the transformer portion includes a low-level signal.