Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.

A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

A wideband polar modulation transmitter includes a power amplifier (PA), a PA driver, a dynamic power supply (DPS), a PA driver V.sub.H controller, and a phase modulator. The phase modulator modulates a radio frequency (RF) carrier by an input phase modulating signal PM(t) to produce a phase modulated RF carrier. Meanwhile, the DPS produces a DPS voltage for the PA that follows an input amplitude modulating signal AM(t). Using the phase modulated RF carrier, the PA driver generates a PA drive signal V.sub.DRV for driving the PA. The PA drive signal V.sub.DRV has a high drive level V.sub.H and a low drive level V.sub.L. The PA driver V.sub.H controller is configured to control the magnitude of the high drive level V.sub.H so that it remains sufficiently high to force the PA to operate in a compressed mode (C-mode) most of the time but lowers the high drive level V.sub.H to force the PA to operate in a product mode (P-mode) during times low-magnitude events occur in the DPS voltage.

A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.

Photo receiver circuits comprising photo diode, a first amplifier, a second amplifier, and a feedback resistor are disclosed. The photo diode receives a light signal producing a photo current and the circuit produces an output voltage proportional to the photo current. In one example, the second amplifier coupled across the photo diode provides a voltage level shift between the input terminal and the output terminal, bootstrapping the parasitic capacitance out.

An electronic circuit comprises an input stage, a gain stage operatively coupled to the input stage, a primary output stage operatively coupled to the gain stage, a replica output stage operatively coupled to the gain stage in parallel to the primary output stage, and a clock circuit. The clock circuit operates the electronic circuit in multiple phases including a sampling phase to disconnect the primary output stage and the replica output stage from the gain stage to obtain an offset voltage, an active phase to reconnect the primary output stage to apply the offset voltage to reduce an offset at the primary output stage, and an intermediate phase to first reconnect the replica output stage to the gain stage prior to the active phase.

A radio frequency (RF) power amplifier (PA) for amplifying an RF signal between a source node and an output node, the RF PA including a silicon substrate with a complementary metal oxide semiconductor (CMOS) N-type transistor with a source region and a drain region fabricated therein. The source region includes the source node of the RF PA and the drain region includes the output node of the RF PA. The RF PA includes a planar resistor fabricated on the surface of the silicon substrate proximal to the drain region of the N-type transistor, wherein the resistor provides a thermal source for heating the RF PA; and a control circuit providing thermal heating to the RF PA by providing power to the planar resistor during RF signal bursts wherein the added thermal heating compensates transient heating within the transistor and results in a linear power amplification operation.

A buffer amplifier comprises a source follower and a feedback amplifier. The feedback amplifier may be configured to control a drain current of the source follower to remain substantially constant independent of a load.

An electronic circuit comprises an input stage, a gain stage operatively coupled to the input stage, a primary output stage operatively coupled to the gain stage, a replica output stage operatively coupled to the gain stage in parallel to the primary output stage, and a clock circuit. The clock circuit operates the electronic circuit in multiple phases including a sampling phase to disconnect the primary output stage and the replica output stage from the gain stage to obtain an offset voltage, an active phase to reconnect the primary output stage to apply the offset voltage to reduce an offset at the primary output stage, and an intermediate phase to first reconnect the replica output stage to the gain stage prior to the active phase.

A buffer stage includes a control circuit. The control circuit includes a voltage generator, a voltage-to-current converter, and a current-to-voltage converter. The voltage generator is configured to generate a compensation voltage. The voltage-to-current converter is configured to convert the compensation voltage into a compensation current. The current-to-voltage converter is configured to convert the compensation current into a recovery compensation voltage. The recovery compensation voltage is arranged for modifying an output voltage of the buffer stage.