Techniques and mechanisms for mitigating signal deterioration in communications between two circuit boards. In an embodiment, a packaged device accommodates coupling to a first circuit board which, in turn, accommodates connection to a second circuit board. In one such embodiment, an amplifier circuit of the packaged device includes an amplifier circuit which comprises a variable resistor and an active circuit element coupled thereto. The device receives via one of the circuit boards a control signal and a voltage which configure the amplifier circuit to provide an impedance matching for communication between the circuit boards. In another embodiment, the device comprises multiple common gate amplifiers which are variously configurable each to provide a respective impedance matching for communications between a motherboard and a dual in-line memory module.

A low noise amplifier circuit includes a first low noise amplifier including a common gate structure cascoded with a parallel common source structure to selectively amplify a band signal among first and second band signals; a second low noise amplifier including a common gate structure cascoded with a parallel common source structure to selectively amplify a band signal among third and fourth band signals; an output DPDT circuit including a first input terminal connected to the first low noise amplifier, a second input terminal connected to the second low noise amplifier, and a first output terminal and a second output terminal for selectively outputting signals input through the first input terminal and the second input terminal; and a control circuit performing an amplification control and a switching control for the first and second low noise amplifiers and the output DPDT circuit in response to a predetermined communications scheme.

A common-source Low Noise Amplifier (LNA) comprises a first spiral inductor coupled to a source of a first transistor, a second spiral inductor coupled to a drain of a second transistor, and a third inductor connecting the first transistor to the second transistor. The third inductor is configurable to enable a first capacitance to be coupled in parallel to form a bandpass filter. The first spiral inductor is configurable to enable a second capacitance to be coupled in parallel to form a resonant circuit. A variation of the LNA further includes a drain of a third transistor coupled to a gate of a fourth transistor with a first width, a source of the third transistor coupled to the resonant circuit, and an oscillator clock configured to operate at a first frequency that enables the third transistor, wherein the third transistor presents a first impedance to the resonant circuit, causing the resonant circuit to have a first bandwidth.

An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.

Disclosed is a differential transimpedance amplifier. The differential transimpedance amplifier includes a common gate amplifier configured to receive an electrical signal from an input node, and a common source amplifier configured to have a feedback resistor and receive the electrical signal form the input node. An output signal of the common gate amplifier and an output signal of the common source amplifier form a differential signal pair. The common gate amplifier and the common source amplifier each includes a load having a transformer which removes an effect of parasitic capacitance

Processes and systems for producing glass fibers having regions devoid of glass using submerged combustion melters, including feeding a vitrifiable feed material into a feed inlet of a melting zone of a melter vessel, and heating the vitrifiable material with at least one burner directing combustion products of an oxidant and a first fuel into the melting zone under a level of the molten material in the zone. One or more of the burners is configured to impart heat and turbulence to the molten material, producing a turbulent molten material comprising a plurality of bubbles suspended in the molten material, the bubbles comprising at least some of the combustion products, and optionally other gas species introduced by the burners. The molten material and bubbles are drawn through a bushing fluidly connected to a forehearth to produce a glass fiber comprising a plurality of interior regions substantially devoid of glass.

Disclosed is a differential transimpedance amplifier. The differential transimpedance amplifier includes a common gate amplifier configured to receive an electrical signal from an input node, and a common source amplifier configured to have a feedback resistor and receive the electrical signal form the input node. An output signal of the common gate amplifier and an output signal of the common source amplifier form a differential signal pair. The common gate amplifier and the common source amplifier each includes a load having a transformer which removes an effect of parasitic capacitance.

Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.

Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.

Disclosed is a low noise amplifier including a current bleeding circuit. The low noise amplifier includes a common gate amplifier, a common source amplifier of which a gate is connected to a source of the common gate amplifier, a symmetric load connected to an output end of the common gate amplifier and an output end of the common source amplifier, and a current bleeding circuit of which one end is connected to the output end of the common source amplifier and another end is connected to the symmetric load, and including an active element and a load corresponding to the symmetric load.