According to one embodiment, in a semiconductor integrated circuit, a first input terminal of an error amplifier is electrically connected to a third node between a second node and a reference potential. A second input terminal of the error amplifier is electrically connected to a reference voltage. An output terminal of the error amplifier is electrically connected to a gate of an output transistor. A first input terminal of a comparator is electrically connected to a fourth node between the second node and the reference potential. A second input terminal of the comparator is electrically connected to the reference voltage. One end of a coupling capacitance is electrically connected to an output terminal of the comparator. A gate of an auxiliary transistor is electrically connected to the other end of the coupling capacitance. A drain of the auxiliary transistor is electrically connected to the second node.

An amplifier circuit comprising: an amplifier; an output limiter for providing a variable impedance comprising: a first and second limiter terminal; a transistor comprising a conduction channel; a first resistor coupled in parallel with the conduction channel; and a capacitor coupled in series with the conduction channel between the conduction channel and the first or second limiter terminal; and a feedback control unit comprising a comparator block configured to provide a control signal to the output limiter based on a comparison of the amplifier output signal and a setting voltage; wherein: the first limiter terminal is coupled to the amplifier input or output; the second limiter terminal receives a reference voltage; and wherein receipt of the control signal at the transistor provides for a variable impedance for the amplifier circuit dependent on the amplifier output signal.

A temperature compensation circuit for a power amplifier is provided, wherein data of circuit configurations corresponding to specific temperatures (including data associated with an output terminal voltage, a bias voltage, an adaptive bias, and a matching impedance of the power amplifier) for the power amplifier is stored in a read-only memory. Therefore, the temperature compensation circuit is capable of reading the data according to a temperature sensing signal to adjust the circuit configuration of the power amplifier accordingly, thereby, in a case of a constant input power of the power amplifier, an output power variance of the power amplifier is within a second interval (e.g., −10%˜+10%) when an environment temperature varies within a first interval. Therefore, the power amplifier has a stable gain.

An embodiment pulse-width modulation (PWM) modulator circuit comprises a first half-bridge stage having a first output node and a second half-bridge stage having a second output node. The first output node and the second output node are configured to have an electrical load coupled therebetween to apply thereto a PWM-modulated output signal. The circuit comprises a differential stage having input nodes configured to receive an input signal applied between the input nodes and produce a differential control signal for the first half-bridge stage and the second half-bridge stage. A current comparator is arranged intermediate the differential stage and the first and second half-bridge stages. The current comparator is configured to produce a PWM-modulated drive signal to drive the half-bridge stages as a function of the input signal applied between the input nodes in the differential stage.

A precharge circuit comprises a gain amplifier, a comparator, a reservoir capacitor, a switch, a current source, and a switching network. The gain amplifier has a gain G1 and receives an input voltage Vrefp. The gain amplifier outputs an amplified voltage G1Vrefp to the comparator, which compares G1Vrefp to a voltage across the reservoir capacitor. The comparator outputs a control signal for the switch based on the comparison. The switch couples the current source to the reservoir capacitor. The current from the current source charges the reservoir capacitor. The switching network couples the reservoir capacitor to an output of the precharge circuit during a first operating mode and provides the input voltage Vrefp to the output during a second operating mode.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.

This application relates to circuitry for monitoring for instability of an amplifier. The amplifier (100) has a first signal path between an amplifier input (IN.sub.N) and an amplifier output (V.sub.OUT) and a feedback path from the output to form a feedback loop with at least part of the first signal path. A comparator (212) has a first input configured to receive a first signal (IN.sub.N) derived from a first amplifier node which is part of said feedback loop and a second input configured to receive a second signal (IN.sub.P) derived from a second amplifier node which varies with the signal at the amplifier input but does not form part of said feedback loop. The comparator is configured to compare the first signal to the second signal and generate a comparison signal (COMP), wherein in the event of amplifier instability the comparison signal comprises a characteristic indicative of amplifier instability.

Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

An apparatus includes a plurality of pixels arranged in an array, a first group of pixels that are arranged in a first direction among the plurality of pixels, a first line to which the first group is connected, a second group of pixels that are arranged in the first direction among the plurality of pixels, and a second line to which the second group is connected. The first line is connected to a first source. The second line is connected to a second source. The apparatus further includes a control unit configured to: (1) perform control to increase a current flowing through the second source while performing control to decrease a current flowing through the first source, or (2) suppress a variation of total amount of flowing current by changing the current flowing through the second source in response to a change in the current flowing through the first source.