Described herein are systems and methods that can adjust the performance of a transimpedance amplifier (TIA) in order to compensate for changing environmental and/or manufacturing conditions. In some embodiments, the changing environmental and/or manufacturing conditions may cause a reduction in beta of a bipolar junction transistor (BJT) in the TIA. A low beta may result in a high base current for the BJT causing the output voltage of the TIA to be formatted as an unusable signal output. To compensate for the low beta, the TIA generates an intermediate signal voltage, based on the base current and beta that is compared with the PN junction bias voltage on another BJT. Based on the comparison, the state of a digital state machine may be incremented, and a threshold base current is determined. This threshold base current may decide whether to compensate the operation of the TIA, or discard the chip.

A linear amplifier includes a pre-amplifier configured to amplify an input differential signal, a post-amplifier configured to amplify an output signal of the pre-amplifier, an amplitude detector configured to detect an amplitude of an output signal of the post-amplifier, and an output voltage corresponding to the detected amplitude, a comparator configured to control a tail current source of the pre-amplifier such that when the output voltage of the amplitude detector is less than or equal to a reference voltage, a tail current of the pre-amplifier is set to a constant value, and when the output voltage of the amplitude detector is larger than the reference voltage, the tail current is reduced to make the output voltage of the amplitude detector equal to the reference voltage.

To suppress voltage variations due to transistor switching noise in a solid-state image sensor including a transistor that initializes a differentiating circuit.

A capacitance supplies a charge corresponding to an amount of variation in a predetermined pixel voltage to a predetermined input terminal. A voltage output unit outputs, as an output voltage, a voltage corresponding to an input voltage at the input terminal from a predetermined output terminal. A reset transistor supplies one of a positive charge or a negative charge during a predetermined period to control the output voltage to an initial value in a case where initialization is instructed. A charge supply unit supplies the other of the positive charge or the negative charge when the predetermined period elapses.

The present disclosure relates to devices and methods for detecting and preventing occurrence of a saturation state in a power amplifier. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.

A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

A driver circuit is disclosed. In an embodiment a drive circuit includes a signal port with a first terminal and a second terminal, a first node and a second node, a comparator with an inverting input, a non-inverting input and an output and an operational amplifier with an inverting input, a non-inverting input and an output, wherein the first terminal is electrically conductively connected with the inverting input of the operational amplifier, wherein the second terminal is electrically conductively connected with the non-inverting input of the comparator, wherein the inverting input of the comparator is electrically conductively connected with the output of the operational amplifier, wherein the first node is electrically conductively connected with the output of the operational amplifier, wherein the inverting input of the comparator is electrically conductively connected with the inverting input of the operational amplifier, and wherein the second node is electrically conductively connected with the non-inverting input of the operational amplifier.

Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

A power amplifier circuit includes a first amplifier transistor having a base or gate for receiving a first signal inputted, the first signal being one balanced signal, a collector or drain for outputting a first amplified signal, and an emitter or source that is electrically connected to ground, a second amplifier transistor having a base or gate for receiving a second signal inputted, the second signal being another balanced signal, a collector or drain for outputting a second amplified signal, and an emitter or source that is electrically connected to the ground, a first variable capacitance electrically coupled between the collector or drain of the second amplifier transistor and the base or gate of the first amplifier transistor, and a second variable capacitance electrically coupled between the collector or drain of the first amplifier transistor and the base or gate of the second amplifier transistor.

In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.

A semiconductor device includes an equalizer for receiving a first signal and outputting a second signal that has been adjusted to compensate for attenuation of the first signal. A filter is connected to the output terminal of the equalizer. A cancellation circuit operates to cancel a DC offset in the output of the equalizer. A processing circuit is configured to control the cancellation circuit to cancel the DC offset according to an output from the filter. The processing circuit sets a time constant for the filter to a first value to permit the cancellation circuit to cancel the DC offset when the equalizer is in a first state, and then sets the time constant to a second value when the equalizer is set to a second state to permit the cancellation circuit to cancel the DC offset when the equalizer is in the second state.