Patent classifications
H03F2200/84
POWER AMPLIFIER CIRCUIT
There is provided a power amplifier circuit with improved operation speed of the protection function against overcurrent or overvoltage. The power amplifier circuit includes an amplifier configured to amplify a radio frequency signal and output the radio frequency signal, a bias current supply circuit configured to supply a bias current to the amplifier, a detection circuit configured to detect whether the current or voltage of the amplifier is equal to or greater than a predetermined threshold; and a draw circuit configured to, when the detection circuit detects that the current or voltage is equal to or greater than the predetermined threshold, draw at least a part of the bias current supplied to the amplifier.
RF AMPLIFIER
An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.
LOW NOISE AMPLIFIER CIRCUIT HAVING MULTIPLE GAINS
A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.
Power amplifier circuit
There is provided a power amplifier circuit with improved operation speed of the protection function against overcurrent or overvoltage. The power amplifier circuit includes an amplifier configured to amplify a radio frequency signal and output the radio frequency signal, a bias current supply circuit configured to supply a bias current to the amplifier, a detection circuit configured to detect whether the current or voltage of the amplifier is equal to or greater than a predetermined threshold; and a draw circuit configured to, when the detection circuit detects that the current or voltage is equal to or greater than the predetermined threshold, draw at least a part of the bias current supplied to the amplifier.
Two-Stage Circuit With Power Supply Rejection Filter
A two-stage circuit includes a differential-to-single-ended first stage with a differential pair of transistors. The first stage includes a current mirror including a diode-connected transistor having an RC circuit coupled to a drain of the diode-connected transistor. The current mirror is configured to mirror a power supply noise current conducted by the RC circuit through a first stage output terminal to a gate of an output transistor in a second stage of the two-stage circuit.
POWER LEVEL DETECTOR CIRCUIT WITH TEMPERATURE-DEPENDENCE REDUCTION
A circuit includes a radio frequency (RF) detector having an RF detector input and an RF detector output. The RF detector is configured to provide a first signal at the RF detector output responsive to a second signal at the RF detector input. The circuit further includes a processing circuit having a processing terminal coupled to the RF detector output. The processing circuit is configured to provide a third signal at the terminal based on scaling the first signal by a factor that is proportional to temperature.
Current amplifier and transmitter using the same
A current amplifier and a transmitter using the same. The current amplifier has a first and second transistor and a voltage level shifting unit. The first transistor has a gate receiving an input current and a drain receiving a driving current. The voltage level shifting unit providing a voltage shift is coupled between the drain of the first transistor and the gate of the second transistor. An output current is generated at the drain of the second transistor.
Accurate sample latch offset compensation scheme
A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.
ACCURATE SAMPLE LATCH OFFSET COMPENSATION SCHEME
A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.
AMPLIFIER CIRCUIT AND METHOD FOR STABILIZING BIAS CURRENT OF AN AMPLIFIER CIRCUIT
An amplifier circuit includes an input terminal, an output terminal, a first transistor, a second transistor, a third transistor, and a voltage tracking circuit. The input terminal would receive an input signal. The output terminal would output the amplified input signal. The control terminals of the first transistor and the second transistor are coupled to one another. The voltage tracking circuit is coupled to a first terminal and the control terminal of the first transistor, a first terminal of the second transistor, and a first terminal of the third transistor. The voltage tracking circuit regulates voltages at the first terminal of the first transistor and the first terminal of the third transistor to be substantially equal during an initial state, and then regulates voltages at the first terminal of the first transistor and the first terminal of the second transistor to be substantially equal during a stable state.