An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.

A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

The disclosure provides an apparatus including: a pair of signal injection transistors each having a gate terminal coupled to a differential reference signal, and a pair of cross-coupled amplifier transistors configured to amplify a voltage of the differential reference signal to yield a voltage-amplified reference signal at a local oscillator (LO) port of a mixer; an electronic oscillator having an oscillation output node coupled to the LO port of the mixer in parallel with the injection-locked buffer, and configured to generate an oscillator output for transmission to the output node based on a back gate bias voltage applied to the electronic oscillator; and an access transistor having a gate coupled to a switching node, and a back gate terminal coupled to the back gate bias voltage, wherein the access transistor is configured to enable or disable current flow through the electronic oscillator in parallel with the injection-locked buffer.

A semiconductor device may include an amplification circuit. The amplification circuit may be configured to generate an output signal and an output bar signal based on a mode signal, first and second control signals, an input signal, and an input bar signal. The amplification circuit may determine voltage levels of the output signal and the output bar signal based on the mode signal and the first and second control signals regardless of the input signal and the input bar signal.

An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.

An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.

A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

An amplifier circuit includes: a first inverter and a second inverter coupled in a cross-coupled form during an amplification operation and suitable for amplifying a voltage difference between a first line and a second line; a first isolation switch suitable for electrically connecting the first line and an output terminal of the first inverter to each other; a second isolation switch suitable for electrically connecting the second line and an output terminal of the second inverter to each other; and an equalizing switch suitable for electrically connecting the output terminal of the first inverter and the output terminal of the second inverter to each other, wherein before the amplification operation, a first offset compensation operation for turning on the second isolation switch and the equalizing switch and a second offset compensation operation for turning on the first isolation switch and the equalizing switch are performed.

An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.