A circuit includes a plurality of first stage integrators. Each of the plurality of first stage integrators includes a first input, a second input, a third input and an output. The first input of each of the plurality of first stage integrators is coupled to a different one of circuit inputs, the second input is coupled to a first reference input, the third input is coupled to a second reference input and the output of each of the plurality of first stage integrators is coupled to the first input of such first stage integrator. The circuit includes a second stage integrator which includes a first input coupled to each of the first inputs of the plurality of first stage integrators, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator.

A circuit includes a plurality of first stage integrators. Each of the plurality of first stage integrators includes a first input, a second input, a third input and an output. The first input of each of the plurality of first stage integrators is coupled to a different one of circuit inputs, the second input is coupled to a first reference input, the third input is coupled to a second reference input and the output of each of the plurality of first stage integrators is coupled to the first input of such first stage integrator. The circuit includes a second stage integrator which includes a first input coupled to each of the first inputs of the plurality of first stage integrators, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator.

A circuit comprises an amplifier network including a first amplifier and a second amplifier and a first transistor having a first base. The first transistor is thermally isolated from the second amplifier. The circuit further comprises a second transistor having a second base. The second transistor is thermally linked to the second amplifier. The circuit further comprises coupling circuitry configured to couple the first base to the second base.

A sensor circuit is provided with a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element, a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit, and a feedback circuit configured to reduce ripple in a signal generated by the chopper-stabilized amplifier circuit. The feedback circuit includes a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate, a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal, and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit.

A sensor circuit is provided with a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element, a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit, and a feedback circuit configured to reduce ripple in a signal generated by the chopper-stabilized amplifier circuit. The feedback circuit includes a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate, a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal, and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

Circuitry, which includes a PA power supply and RF PA circuitry, is disclosed. The RF PA circuitry includes a group of RF PAs and a group of PA decoupling circuits. The group of RF PAs includes a first RF PA and a second RF PA. The group of PA decoupling circuits includes a first PA decoupling circuit and a second PA decoupling circuit. The PA power supply provides a first PA power supply output signal to at least one of the group of RF PAs and to at least one of the group of PA decoupling circuits. The first PA decoupling circuit is coupled across the first RF PA, is programmable, and at least partially decouples the first RF PA from other circuitry. The second PA decoupling circuit is coupled across the second RF PA and at least partially decouples the second RF PA from other circuitry.

Circuitry, which includes a PA power supply and RF PA circuitry, is disclosed. The RF PA circuitry includes a group of RF PAs and a group of PA decoupling circuits. The group of RF PAs includes a first RF PA and a second RF PA. The group of PA decoupling circuits includes a first PA decoupling circuit and a second PA decoupling circuit. The PA power supply provides a first PA power supply output signal to at least one of the group of RF PAs and to at least one of the group of PA decoupling circuits. The first PA decoupling circuit is coupled across the first RF PA, is programmable, and at least partially decouples the first RF PA from other circuitry. The second PA decoupling circuit is coupled across the second RF PA and at least partially decouples the second RF PA from other circuitry.

A loudspeaker real-time state variable prediction system may include a loudspeaker having a voice coil and a magnet, and a non-linear excursion model configured to estimate non-linear excursion of the loudspeaker. The system may further include a thermal model configured to utilize thermal parameters and frequency based on at least one thermal property of the loudspeaker, and a gain adjustment thermal limiter configured to apply a gain reduction an incoming audio signal to protect the loudspeaker from thermal overload.