An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.

A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.

Systems, methods, apparatus, and articles of manufacture to control audio playback devices are disclosed. An example first playback device includes a speaker driver, a processor, and a computer readable medium including a set of instructions that, when executed by the processor, cause the first playback device to implement a method. The example method includes receiving, from a first audio information source, first audio information. The example method includes playing back the first audio information. The example method includes receiving, from a second audio information source, (i) a first message, and (ii) second audio information. Based on the received first message, the example method includes (i) determining that the first playback device and a second playback device are to playback the second audio information; (ii) stopping play back of the first audio information; (iii) playing back, via the speaker driver, the second audio information; and (iv) sending the second audio information to the second playback device.

The present application relates to a gain control method and an apparatus, comprising an automatic gain controller. An input power of a PSS in an input signal is detected in real time, a rated power of a downlink PSS that acts as a gain control threshold of the automatic gain controller is acquired, and the automatic gain controller is controlled to adjust a value of gain attenuation according to magnitudes of the input power of the PSS and the rated power of the downlink PSS, which is used to adjust an uplink gain and a downlink gain.

According to one embodiment, in a semiconductor integrated circuit, the second circuit samples an amplitude of the output second signal at a plurality of timings every given cycle in a period corresponding to a second period of the pattern. The second circuit controls a parameter relating to the frequency characteristic for the first circuit according to a first magnitude relation and a second magnitude relation. The first magnitude relation is a relation between an absolute value of a first amplitude and a first threshold. The first amplitude is an amplitude sampled at a first timing among the plurality of timings. The second magnitude relation is a relation between an absolute value of a second amplitude and the first threshold. The second amplitude is an amplitude sampled at a second timing. The second timing is a timing after the first timing among the plurality of timings.

Quadrature error correction (QEC) for radio transceivers are provided herein. In certain embodiments, a transceiver includes an in-phase (I) signal path including a first controllable amplifier coupled to a first data converter, and a quadrature-phase (Q) signal path including a second controllable amplifier coupled to a second data converter. The transceiver further includes a QEC circuit operable to correct for a quadrature error between the I signal path and the Q signal path by adjusting a gain of the first controllable amplifier and/or a gain of the second controllable amplifier.

The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.

According to one embodiment, a semiconductor device includes the following configuration. A detection circuit detects a state of a clock signal. An amplification circuit changes a gain based on the state of the clock signal detected by the detection circuit. An amplification circuit amplifies a first voltage with the gain and outputs a second voltage obtained as a result of amplification. A conversion circuit converts the second voltage output from the amplification circuit to first data. An isolation circuit includes a driver and a receiver electrically isolated from the driver. The driver transmits a signal corresponding to the first data to the receiver. The receiver outputs second data corresponding to the signal transmitted from the driver. The output circuit outputs the second data output from the isolation circuit.