An RF power limiter and ESD protection circuit has a set of two CMOS FETs each configured to perform a diode function with a defined forward voltage and arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal. When an RF signal is applied symmetrically to the input terminal and ground terminal it becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured CMOS FETs. In the ESD protection mode one of the CMOS FETs acts as a grounded gate NMOS transistor with SCR action to provide for mitigation of voltage and current over-stress of transistors utilized in RF transceiver circuits. Generally, the circuit architectures allow input power levels to be limited to an extent that reliable operation can be maintained.

Provided are a distance-measuring device and a method thereof. The distance-measuring device detects light reflected by an object and converts the light into electrical signals, outputs a saturation signal equal to or greater than a reference value from among the electrical signals, detects a peak using the saturation signal, and measures a distance to the object using the peak.

Provided are a distance-measuring device and a method thereof. The distance-measuring device detects light reflected by an object and converts the light into electrical signals, outputs a saturation signal equal to or greater than a reference value from among the electrical signals, detects a peak using the saturation signal, and measures a distance to the object using the peak.

A decoder for a wireless charging transmitter and a wireless charging transmitter using the same are provided in the present invention. In order to adapt the wide range of the received signal from the wireless charging receiver, which usually results in the error of the decode, the feedback circuit of the wireless charging transmitter is changed, so that the signal in a certain swing is amplified by an original gain, and the signal out of the certain swing is amplified by a limited gain. Therefore, the amplified signal is able to show the characteristic of the original received signal. Thus, the accuracy of decoding is increased.

An apparatus includes an input port, an output port, a first bias input, a first shunt PIN diode, a first radio frequency (RF) choke inductor, and a first direct current (DC) blocking capacitor. The input port may be connected to the output port, a first terminal of the first shunt PIN diode, and a first terminal of the first RF choke inductor. A second terminal of the first RF choke inductor is connected to a first terminal of the first DC blocking capacitor and the first bias input. A second terminal of the first shunt PIN diode and a second terminal of the first DC blocking capacitor are connected to a circuit ground potential. A first bias voltage having a magnitude lower than a knee voltage of the first shunt PIN diode is applied at the first bias input.

An apparatus includes an input port, an output port, a first bias input, a first shunt PIN diode, a first radio frequency (RF) choke inductor, and a first direct current (DC) blocking capacitor. The input port may be connected to the output port, a first terminal of the first shunt PIN diode, and a first terminal of the first RF choke inductor. A second terminal of the first RF choke inductor is connected to a first terminal of the first DC blocking capacitor and the first bias input. A second terminal of the first shunt PIN diode and a second terminal of the first DC blocking capacitor are connected to a circuit ground potential. A first bias voltage having a magnitude lower than a knee voltage of the first shunt PIN diode is applied at the first bias input.

A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a diode limiter semiconductor structure have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. The thin intrinsic region PIN diode can be optimized for low level turn on and flat leakage, and the thick intrinsic region PIN diode can be optimized for low capacitance, good isolation, and high incident power levels. This configuration is not limited to two stage solutions, as additional stages can be used for higher incident power handling.

An RF power limiter and ESD protection circuit has a set of two CMOS FETs each configured to perform a diode function with a defined forward voltage and arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal. When an RF signal is applied symmetrically to the input terminal and ground terminal it becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured CMOS FETs. In the ESD protection mode one of the CMOS FETs acts as a grounded gate NMOS transistor with SCR action to provide for mitigation of voltage and current over-stress of transistors utilized in RF transceiver circuits. Generally, the circuit architectures allow input power levels to be limited to an extent that reliable operation can be maintained.

A distributed amplifier system constituted of: an input transmission line exhibit a plurality of sections; an output transmission line; an amplifier stage, an output of the amplifier stage coupled to the output transmission line and an input of the amplifier stage coupled to the input transmission line between a respective pair of the plurality of sections; a PIN diode coupled between a first end of the input transmission line and a common potential; and a circuitry coupled between a second end of the input transmission line and the common potential, the second end opposing the first end, such that there is a direct current (DC) flow through the first unidirectional electronic valve, the input transmission line and the circuitry.

An active limiting system that is suitable to protect a low noise amplifier against the high power signals received from a signal input includes, at least one first switch, source of which is connected to a gate voltage; at least first resistor which is connected between the gate and source of the first switch; at least one second resistor, which is connected between a drain voltage and drain of the first switch; at least one second switch, source of which is connected to said drain voltage and drain of which is connected to a signal input; at least one third resistor which is connected between the drain of the first switch and gate of the second switch; at least one first filtering element, which blocks DC currents/voltages and which is connected between the source of the second switch and ground.