The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

A variable capacitance device includes: a first and second terminal for signals; a plural, even number of variable capacitance elements connected in-series between the first and second terminal; a third and fourth terminal for receiving a same voltage; a fifth and sixth terminal for grounding; a plurality of first resistors connected to either the third or fourth terminal on one end; and a plurality of second resistors connected to either the fifth or sixth terminal on one end. With respect to a series of successive nodes beginning with the first terminal and ending with the second terminal, respective other ends of a pair of the first resistors are connected to every other node, and respective other ends of a pair of the second resistors are connected to the remaining every other node, such that the pairs of first and second resistors are alternately connected to the series of successive nodes.

A variable capacitance device includes: a first and second terminal for signals; a plural, even number of variable capacitance elements connected in-series between the first and second terminal; a third and fourth terminal for receiving a same voltage; a fifth and sixth terminal for grounding; a plurality of first resistors connected to either the third or fourth terminal on one end; and a plurality of second resistors connected to either the fifth or sixth terminal on one end. With respect to a series of successive nodes beginning with the first terminal and ending with the second terminal, respective other ends of a pair of the first resistors are connected to every other node, and respective other ends of a pair of the second resistors are connected to the remaining every other node, such that the pairs of first and second resistors are alternately connected to the series of successive nodes.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

A device comprises a first capacitor block comprising a plurality of first capacitors connected in a first configuration, a second capacitor block comprising a plurality of second capacitors connected in the first configuration, a third capacitor block comprising a plurality of third capacitors connected in a second configuration, a fourth capacitor block comprising a plurality of fourth capacitors connected in the second configuration, a first switch connected between the first capacitor block and the second capacitor block, a second switch connected between the third capacitor block and the fourth capacitor block, a third switch connected between the first capacitor block and the fourth capacitor block and a fourth switch connected between the third capacitor block and the second capacitor block.