An LC parallel resonant element includes a first planar or substantially planar conductor on a first base material layer and second and third planar or substantially planar conductors on second and third base material layers. The first and third planar or substantially planar conductors extend over nearly the entire surfaces of the first and third base material layers. The second planar or substantially planar conductor extends over nearly the entire length of the second base material layer in a second direction such that a space from the other end portion of two end portions of a multilayer body in a first direction is provided. The first and third planar or substantially planar conductors are connected to each other by interlayer conductors near the other end portion of the multilayer body. The first and second planar or substantially planar conductor are connected to each other by interlayer conductors near one end portion of the multilayer body.

The variable capacitance device includes one or more of directional elements inserted between the third and fourth terminals that allow current to pass only in prescribed directions, such that a diagram formed of current paths from the third terminal to the fourth terminal for the plurality of third-terminal side resistors and the plurality of fourth-terminal side resistors when the third terminal is biased higher than the fourth terminal is line-symmetric to a diagram formed of current paths from the fourth terminal to the third terminal for the plurality of third-terminal side resistors and the plurality of fourth-terminal side resistors when the fourth terminal is biased higher than the third terminal, with respect to the serial chain of variable capacitance elements between the first and second terminals.

The variable capacitance device includes one or more of directional elements inserted between the third and fourth terminals that allow current to pass only in prescribed directions, such that a diagram formed of current paths from the third terminal to the fourth terminal for the plurality of third-terminal side resistors and the plurality of fourth-terminal side resistors when the third terminal is biased higher than the fourth terminal is line-symmetric to a diagram formed of current paths from the fourth terminal to the third terminal for the plurality of third-terminal side resistors and the plurality of fourth-terminal side resistors when the fourth terminal is biased higher than the third terminal, with respect to the serial chain of variable capacitance elements between the first and second terminals.

A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

A programmable resistor can provide discrete logarithmic (linear-in-dB) gain control. It can include multiple like programmable resistor subnetworks or cells, such as can be connected in parallel, such as according to a decoding scheme. The subnetworks can be configured to cover a subrange such as [0 dB, 6 dB) relative to the maximum resistance value. Coarse increments of 6 dB can be further added to this range by successively doubling the number of subnetworks that are connected in parallel. An additional decoder help ensure a linear control curve, free of dead zones or other nonlinearities. The programmable resistor can be suitable for use in such circuits as programmable-gain amplifiers, filters, or more complex networks, such as where the resistance can be programmed as a function of a digital code. An example including a tuning circuit for a variable gain active filter is described.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.