A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

A filter circuit includes a filter that is disposed on a path connecting a common terminal and an input output terminal and uses a first frequency band as a pass band, a filter that is disposed on a path connecting the common terminal and an input output terminal and uses a second frequency band different from the first frequency band as a pass band, and a phase adjustment circuit that has an input terminal connected to the path and an output terminal connected to the path, and adjusts a phase of a signal in the first frequency band input from the path and outputs a signal having a phase different from a phase of the signal in the first frequency band to the output terminal, wherein the path and the path are paths through which a received signal passes.

An illustrative SerDes receiver includes: a front-end filter, a precomputation unit, a selection element, and a controller. The front end filter converts a receive signal into a linearly-equalized signal. The precomputation unit accepts the linearly-equalized signal with or without a subtracted feedback signal, and employs a set of comparators with threshold values that depend on a first post-cursor ISI value F.sub.1, the set of comparators operating to generate a set of tentative symbol decisions. The selection element derives a selected symbol decision from each set of tentative symbol decisions, thereby deriving a sequence of symbol decisions from the receive signal. The controller constrains F.sub.1 if the receive signal uses a PAM4 signal constellation, setting F.sub.1 to equal zero if the receive signal is conveyed via a low-loss channel and to equal one if the receive signal is conveyed via a high-loss channel.

According to one embodiment, in a semiconductor integrated circuit, a variable delay circuit is electrically connected to the correction circuit and configured to change a delay amount of the second clock. An adjustment circuit is electrically connected to a summer circuit. The adjustment circuit is configured to perform sampling of values in a plurality of edge periods and values in a plurality of data periods of data output from the summer circuit, and adjust a delay amount of the variable delay circuit such that timing of the second clock supplied from the variable delay circuit to the correction circuit becomes close to target timing according to a plurality of sampling results.

Devices and methods for finite impulse response (FIR) feed forward equalization (FFE) at a transmitter are provided. A voltage-mode driver circuit has a main driver and an equalization driver. The main driver drives the digital output signal based on a received digital input signal. The equalization function of the equalization driver is enabled or disabled for a short duration of time to provide at least one of FIR equalization and pre-emphasis to the digital output signal. Pre-emphasis is effected by enabling a low-resistance path of the equalization driver based on the digital input signal such that, when the low-resistance path is enabled, it reduces the transmission resistance for a short period of time.

Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.

The present disclosure relates to an encoder and an encoding method thereof, as well as a decoder and a decoding method thereof, which can be used to reduce the number of wires necessary for data transmission and transmit more data at a faster speed with the same number of wires, thereby improving the efficiency of data transmission. The encoder may comprises two input terminals configured to receive two input signals simultaneously, each input terminal comprises a wire identifying a positive voltage and a wire identifying a negative voltage; and a plurality of output terminals, wherein each output terminal comprises a wire identifying a positive voltage and a wire identifying a negative voltage, a combination of the two input signals corresponds to one of the plurality of output terminals, and the output terminal to which the current combination of the two input signals corresponds is configured to output signals through the two wires of the output terminal.

An integrated circuit (IC) memory device includes receiver circuitry to receive write data from a memory controller. The receiver circuitry includes equalization circuitry having at least one tap to equalize the write data. The equalization circuitry includes a tap weight adapter circuit to adaptively generate a tap weight for the tap from an edge analysis of previously received write data.

Embodiments include apparatuses, methods, and systems including a decision feedback equalizer (DFE). The DFE includes a first summer circuit, a second summer circuit, a decision circuit, and a tap-delay line including a number of delay elements. The first summer circuit is to add together an analog signal and a first set of weighted feedback taps {h(j+1), . . . h(m)} of time delayed signals of a detected symbol to generate a first summand. The second summer circuit is to add together a second set of weighted feedback taps {h(k+1), h(n)} of time delayed signals of the detected symbol to generate a second summand. The decision circuit is to receive at least the first summand and the second summand, to generate the detected symbol based on a sum including the first summand and the second summand. Other embodiments may also be described and claimed.

A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.