A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

This invention discloses an active load generation circuit and a filter. The active load generation circuit includes a transistor, a voltage control circuit, a voltage offset and tracking circuit, and a temperature sensing circuit. The transistor provides an impedance and includes a control terminal and an input terminal. The control terminal receives a control voltage, the input terminal receives an input signal, and the impedance is associated with the control voltage. The voltage control circuit generates an intermediate voltage according to a power supply voltage and a first reference voltage. The voltage offset and tracking circuit generates the control voltage according to the input signal and the intermediate voltage such that the control voltage varies with the input signal. The temperature sensing circuit senses an ambient temperature of the active load generation circuit and adjusts the first reference voltage according to the ambient temperature.

Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

A system for thermally protecting an amplifier driving a capacitive load may include a low-pass filter configured to filter, with a variable cutoff frequency, an input signal to generate a filtered input signal, wherein the amplifier is configured to receive the filtered input signal and amplify the filtered input signal to generate a driving signal to the capacitive load and a controller configured to receive a real-time estimate of a temperature associated with the amplifier and vary the variable cutoff frequency as a function of the temperature.