Systems, devices, and methods related to a sample rate converter (SRC) for implementing a rate conversion R are provided. The SRC receives input samples at an input rate F.sub.in and outputs samples at an output rate F.sub.out=F.sub.in×R, where R is a fractional value greater than 1. The SRC includes a plurality of filters to process the received input samples and a multiplier-adder block to generate the output samples based on respective delta values and outputs of the plurality of filters. The SRC further includes a plurality of buffers to buffer samples between the plurality of filters and the multiplier-adder block based at least in part on N buffer read pointers, where N is an integer greater than 1. The SRC further includes resampler control circuitry to generate N delta values of the delta values and the N buffer read pointers in parallel based on R.

A microprocessor system comprises a computational array and a hardware data formatter. The computational array includes a plurality of computation units that each operates on a corresponding value addressed from memory. The values operated by the computation units are synchronously provided together to the computational array as a group of values to be processed in parallel. The hardware data formatter is configured to gather the group of values, wherein the group of values includes a first subset of values located consecutively in memory and a second subset of values located consecutively in memory. The first subset of values is not required to be located consecutively in the memory from the second subset of values.

An electric digital received signal obtained from a received optical signal is segmented into blocks of a certain length with an overlap of a length determined in advance with an adjacent block. Fourier transformation is performed for each of the blocks. The blocks subjected to the Fourier transformation are stored consecutively in time series, a coefficient determined based on a wavelength dispersion compensation amount according to one of frequency positions and a delay amount according to one of the frequency positions and one of time positions is applied to each of frequency component values included in a plurality of the stored blocks, and the blocks to which the coefficient has been applied and which are obtained by adding up the frequency component values to which the coefficient has been applied for each of the frequency positions are generated. Inverse Fourier transformation is performed on the generated blocks to which the coefficient has been applied. A part of the overlap subjected to the inverse Fourier transformation is removed.

A method for signal processing, receiving a time domain signal having a sample-rate Fs and generating N time domain signal bands, each having a bandwidth equal to Fs/N. Receiving the N signal bands and transforming a first time domain signal band to a frequency domain at a first resolution and a second time domain signal band to the frequency domain at a second resolution, where the first resolution may be different from the second resolution. Determining one or more first filter coefficients using the frequency domain components from the first signal band and one or more second filter coefficients using the frequency domain components from the second signal band. Transforming the first and second filter coefficients from the frequency domain to a time domain. Applying the first and second time domain filter coefficients to the first and second time domain signals, respectively.

An apparatus for transmitting ultrasonic waves, the apparatus including a microchip (300) for driving a resonant circuit and a resonant circuit which is at least one of an inductance (L) capacitance (C) circuit (LC tank), an antenna and a piezoelectric transducer. The microchip (300) is a single unit which includes a plurality of interconnected embedded components and subsystems including at least an oscillator (315), a pulse width modulation (PWM) signal generator subsystem (329), an analogue to digital converter (ADC) subsystem (318) and a digital to analogue converter (DAC) subsystem (327).

Decimation filter circuitry may include polyphase filtering structures that perform decimation filtering using filter coefficients. Generic polyphase filtering structures do not take advantage of symmetries between the corresponding filter coefficients. If desired, the arrangement of the polyphase filtering structures in the decimation filter circuitry may be optimized relative to generic polyphase filtering structures to take advantage of corresponding filter coefficient symmetries, thereby allowing for implementation of dynamic decimation ratios and a dynamic number of channels while reducing the number of required multipliers by half with respect to generic polyphase filters. Decimation filters may include pre-adder circuitry that receives first and second portions of a data stream and adds corresponding samples from the first and second portions to generate pre-added values. Convolving circuitry may generate filtered output data by convolving the pre-added values with corresponding filter coefficients based on symmetry of the filter coefficients.

Methods and devices are described for reducing the audible effect of pre-responses in an audio signal. The pre-responses are effectively delayed by employing a digital non-minimum-phase filter, which includes a zero lying outside the unit circle in its z-transform response. This zero is not paired with another zero at a reciprocal position inside the unit circle, as this would linearise the phase modification. The filtering can introduce a greater group delay at the pre-response frequency than at a low frequency, such as 500 Hz or even 0 Hz. The technique can be used to reduce pre-responses in an existing audio signal and also to pre-empt pre-responses that would be introduced to the audio signal by subsequent processing.

An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Systems and methods are provided for channelizing. A first stage can provide a WOLA filter bank that can apply a single multiplier resource to perform window weighting for multiple WOLA filter banks. The first stage can remove mixer-based post FFT adjustment and provide equal functionality with a particular modification of tuning mixers at inputs of second stage FIR paths. The first stage can include a variable decimation, using a particular implementation of variable sample block size.