A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.

A digital phase shifter includes a logic control circuit, at least four current digital-to-analog converters, at least four amplifiers, and a vector summation circuit. The logic control circuit generates four N-bit digital phase shift control signals according to an (N+2)-bit digital control source signal, and respectively inputs the four N-bit digital phase shift control signals to the four current digital-to-analog converters. The four current digital-to-analog converters are respectively connected in series with the four amplifiers, to implement selection and amplification on four orthogonal input signals, and the vector summation circuit synthesizes amplified signals that are output by the four amplifiers, to obtain a signal having a 360 degree () phase shift range.

A phase control signal generation device generating a phase control signal for each of frequency bands for an audio signal converted into a frequency domain, the phase control signal generation device comprising: a setting change means that is able to change setting of a propagation delay time for each of predetermined frequency bands; a difference obtaining means that obtains a difference between propagation delay times before and after setting change; an updating means that updates a phase control amount of the frequency band for which the propagation delay time is changed, based on the obtained difference; and a phase control signal generating means that generates a phase control signal of each frequency band by performing a smoothing process for the phase control amount in a frequency domain using the updated phase control amount.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

An embodiment of passive phase shifter comprises a ground shield, a pair of ground walls electrically connected to the ground shield having a first height above the ground shield; and a signal line positioned between the ground walls and electrically isolated from the ground shield. The signal line may comprise an intermediate signal line separated a second height above the ground shield; a top signal line separated from the intermediate signal line at a third height above the ground shield and electrically connected to the intermediate signal line by one or more conductive vias; and a plurality of blocks positioned between and electrically isolated from the intermediate signal line and the top signal line.

An embodiment of passive phase shifter comprises a ground shield, a pair of ground walls electrically connected to the ground shield having a first height above the ground shield; and a signal line positioned between the ground walls and electrically isolated from the ground shield. The signal line may comprise an intermediate signal line separated a second height above the ground shield; a top signal line separated from the intermediate signal line at a third height above the ground shield and electrically connected to the intermediate signal line by one or more conductive vias; and a plurality of blocks positioned between and electrically isolated from the intermediate signal line and the top signal line.

A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.

A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.

An oscillator architecture with pulse-edge tuning. The oscillator includes a signal generator generating at least two signal frequencies, and a logic circuit (such as an AND gate) that combines the signal frequencies to generate a corresponding oscillator signal. The logic circuit includes a pull-up PMOS transistor coupled to a high rail, and a pull-down NMOS transistor coupled to a low rail. Duty cycle tuning/correction circuitry includes high and low side tuning FETs: a high-side tuning PMOS transistor is coupled between the high rail and a source terminal of the pull-up PMOS transistor, and a low-side tuning NMOS transistor is coupled between the low rail and a source terminal of the pull-down NMOS transistor. Both tuning FETs are controlled for operation as a variable resistor by respective high-side and low-side DACs (digital to analog converters) configure to provide a tuning control signals to the tuning FETs (variable resistance) based on respective input digital tuning/correction signals. In an example application, the oscillator design is adapted for a direct conversion RF transmit chain including an I-Path and a Q-Path: the signal generator generates I and Q differential signal frequencies, and each signal frequency is generated by a separate logic circuit (such as an AND gate), including pulse-edge tuning/correction circuitry.