Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.

A circuit for processing an input-signal voltage comprises a first comparator comprising a first-comparator sense node and a reference capacitance that is coupled to the first-comparator sense node, a second comparator comprising a second-comparator sense node, and a comparator select switch coupled between a path input terminal of the circuit and the first-comparator sense node and the second-comparator sense node. A method of processing at least one input-signal voltage using at least one associated threshold voltage in a circuit, wherein a plurality of comparators comprises more comparators than there are path input terminals coupled to path output terminals, comprises selectively making a coupling via one comparator of two comparators provided in parallel to form a coupling path from the path input terminal to an associated path output terminal, while breaking the coupling via the other comparator.

The present disclosure relates to a head-wearable hearing device which comprises a magnetic inductance antenna having a predetermined resonance period for receipt of wireless data signals and a switched capacitor DC-DC converter configured for converting a DC input voltage into a higher or lower DC output voltage in accordance with a clock signal. The charge pump circuit is configured to charge an output capacitor by output current pulses where the output current pulses at least comprise first and second consecutive output current pulses having a mutual pulse delay corresponding to substantially one-half of the predetermined resonance period of the magnetic inductance antenna.

A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode.

A system may include a plurality of processing paths having a first path configured to generate a first digital signal based on an analog input signal and a second path configured to generate a second digital signal based on the analog input signal, the second path having a high-pass filter for filtering the analog input signal prior to the analog input signal being processed by the remainder of the second path, and the high-pass filter having a corner frequency. Control circuitry may be configured to determine frequency-dependent weighted proportions of the first and second digital signals to be combined into an output digital signal based on a characteristic of the analog input signal. Frequency-dependent weighted proportions may be such that the digital output signal includes spectral content of the first digital signal below the corner frequency to account for spectral content of the second digital signal below the corner frequency being filtered.

A system may include an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance, and control circuitry configured to determine a difference between the input signal and the output signal and switch between modes of the plurality of modes when the difference is less than a predetermined threshold.

An apparatus comprises: a first circuitry to charge first and second capacitors to a predetermined voltage level; a second circuitry to discharge the first capacitor through a diode at a first time; a third circuitry to discharge the second capacitor through the diode at a second time, wherein the second time is greater than the first time; a comparator to compare a first voltage of the first capacitor with a second voltage of the second capacitor; and logic to adjust a scaling factor applied to the second voltage according to an output of the comparator.

A switch control circuit includes: a clock generating circuit that generates one or more periodic signals having a predetermined cycle; a clock adjusting circuit that generates one or more control signals by adjusting a bias voltage of the one or more periodic signals and changing an ON period of the one or more periodic signals; and at least one switching circuit including one or more switches that are switched to ON if respective amplitudes of the generated one or more control signals is equal to or higher than a threshold value and that are switched to OFF if the respective amplitudes of the generated one or more control signals is less than the threshold value.

A switched-capacitor converter includes a rectifier at the output, a plurality of legs coupled between the input and the rectifier, and a controller. Each leg of the switched-capacitor converter includes a capacitor, and a switch device is connected to each leg. A first group of the legs is coupled to a first branch of the rectifier, and a second group of the legs is coupled to a second branch of the rectifier. The controller alternates switching of the first and second groups of legs after startup, to transfer energy from the input to the output during a first part of each switching cycle via the first group of legs and to ground during a second part of each switching cycle via the second group of legs. The controller or a current limited source provides for pre-charging of at least one of the capacitors during startup.

A circuit for processing an input-signal voltage comprises an input capacitance coupled between an input node of the circuit and a sense node of a comparator and a reference capacitance coupled to the sense node of the comparator. A method for processing an input-signal voltage comprises configuring a reference capacitance coupled to an input capacitance; during a charge phase, charging the reference capacitance to a first-level reference voltage; and, during an operative phase, setting the input capacitance to an input-signal voltage to obtain, at the sense node, a sense voltage.

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.