A delta-sigma modulator includes a first integrator configured to integrate a sum of an input signal and a first feedback signal, a second integrator configured to integrate a sum of an output value of the first integrator and a second feedback signal, a first FIR filter circuit configured to perform a first FIR filtering on an output modulation signal and a delay modulation signal and feeds back the signals to stage prior to the first integrator, and a second FIR filter circuit configured to perform a second FIR filtering on the output modulation signal and the delay modulation signal and feeds back the signals to a stage prior to the second integrator.

A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.

A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.

A FIR filter (15), comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first transconductance device (30a) configured to generate a first current signal (i1) proportional to the input signal; a first analog switch (41a) commuted in n by a first digital gate signal (1) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor (45a) when the first digital gate signal has a second value; characterized in that the first digital gate signal (1) comprises a periodic series of pulses, wherein the pulses have widths proportional to the filter coefficients.

A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.

A radio frequency transmitter includes a transmit circuit configured to generate a transmit signal; a receive band rejection filter comprising a capacitor and an inductor resonating with each other to reject a receive frequency band from the transmit signal, wherein a ratio value of a capacitance value of the capacitor to an inductance value of the inductor is within a predetermined range; and a power amplifying circuit configured to amplify the transmit signal through the receive band rejection filter.

The present disclosure provides an integrating circuit and a signal processing module. The integrating circuit comprises an operational amplifier; an integrating capacitor, coupled to an output terminal and a first input terminal of the operational amplifier; and an adjustable resistance module, coupled between the first input terminal of the operational amplifier and an integrating input terminal of the integrating circuit. The adjustable resistance module receives a plurality of first control signals, to adjust a resistance value of the adjustable resistance module. The present disclosure may realize the noise brought by sidelobe to enhance the SNR, and reduce the power consumption and complexity of the overall circuit.

A physical quantity detection device includes a switched capacitor filter circuit having a first sample-and-hold circuit adapted to sample and hold a first signal, which is based on an output signal of a physical quantity detection element, an amplifier circuit to which an output signal of the first sample-and-hold circuit is input, and a first switched capacitor circuit to which a first output signal of the amplifier circuit is input, wherein an output signal of the first switched capacitor circuit is input to the amplifier circuit, and an A/D conversion circuit adapted to perform an A/D conversion on an output signal of the switched capacitor filter circuit.

Disclosed examples include switched capacitor integrator circuits including an amplifier, a feedback capacitor, a sampling capacitor, a loading capacitor and a switching circuit, along with a controller that operates the switching circuit to sample an input signal to the sampling capacitor during a sample portion of a given sample and hold cycle, to couple the sampling capacitor to an amplifier input during a first hold portion of each sample and hold cycle, and to couple the sampling capacitor and the loading capacitor to the amplifier input in a second hold portion of each sample and hold cycle to reduce the bandwidth and power consumption by the integrator circuit.

A comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter (ADC), a decoder, and a switch-capacitor network. The ADC is coupled to the first input terminal and the second input terminal and includes a plurality of comparators. The decoder is coupled to the ADC. The switch-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The voltage of the first output terminal and the voltage of the second output terminal do not exceed a target range.