A system, method and computer readable medium are provided. One system includes a transmit antenna, at least one receive antenna, and a controller configured to operate the transmit antenna and the at least one receive antenna to acquire coupled signal information from a device under test. The system also includes a processor configured to approximate a shape of a structure within the device under test using changes in resonance determined from the coupled reflected signal information and caused by different materials forming the structure.

Systems and methods for performing automatic frequency control are provided. Instead of relying on individual frequency tuners for each channel of a multi-channel receiver system, the present subject matter uses a single frequency tuner for receiving each channel of the multi-channel receiver system. A locked demodulator may be designated as a reference demodulator and frequency offset values associated with the reference demodulator may be applied to other demodulators of the multi-channel receiver. These frequency offset values may be used by individual demodulators of each channel for correcting corresponding frequency offsets.

A method of controlling a tunable passive component in a pulse width modulation controlled switched mode power supply (SMPS) having a power input and an output with tunable passive component power filter. The method includes operably connecting and supplying power relative to a circuit ground to a DC bus, converting a voltage on the DC bus to an output voltage by operating a first switching device and a second switching device at a selected frequency, and filtering the output voltage with a tunable output filter, the tunable output filter including a tunable passive component responsive to a control function circuit configured to automatically tune the tunable passive component value based on a voltage associated with operation of the power supply to maintain resonance of the tunable output filter at about the selected frequency.

Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

Systems and methods for performing automatic frequency control are provided. Instead of relying on individual frequency tuners for each channel of a multi-channel receiver system, the present subject matter uses a single frequency tuner for receiving each channel of the multi-channel receiver system. A locked demodulator may be designated as a reference demodulator and frequency offset values associated with the reference demodulator may be applied to other demodulators of the multi-channel receiver. These frequency offset values may be used by individual demodulators of each channel for correcting corresponding frequency offsets.

In some examples, one or more processors configured by executable instructions may receive an audio signal and data to embed in the audio signal. For example, the data may be received dynamically from one or more data sources. The one or more processors may embed the received data in real time into the audio signal as embedded data based at least in part on controlling a phase angle of a selected frequency component of the audio signal. For instance, the embedded data may include at least one of text, a bar code, a quick response code, an image, a uniform resource locator (URL), or multimedia content. Additionally, the one or more processors may send the audio signal with the embedded data over a network to a plurality of electronic devices that include respective decoders for extracting the embedded data from the audio signal.

In some examples, an audio signal is received and divided into a plurality of frames. Frequency domain data of the audio signal may be generated for an individual frame of the plurality of frames. For example, the frequency domain data may include a plurality of sinusoidal components. Data may be embedded into a selected sinusoidal component selected from the frequency domain data of the individual frame by controlling a phase angle of the selected sinusoidal component to represent a selected bit of the data. For instance, a first range of the phase angle may represent a first type of bit and a second range of the phase angle may represent a second type of bit.

An antenna impedance tuner can include first and second nodes, a bypass path, first and second series capacitance paths, and an inductance path, with each path being implemented between the first and second nodes and including a switch configured to allow the path to couple or uncouple the first and second nodes. The tuner can further include first and second shunt paths, with each shunt path being implemented between the second node and ground and including a switch configured to allow the shunt path to couple or uncouple the second node and the ground. The tuner can further include a switchable grounding path implemented along the inductance path and configured to allow the inductance path to function as a series inductance path between the first and second nodes, or as a shunt inductance path between the ground and a node along the inductance path.

Provided an active suppression controller with an adaptive algorithm capable of tracking the fluctuation of multi-fundamental frequencies and correcting them while the deviation is divergence based on the DXHS (Delayed-X Harmonics Synthesizer). It includes a controller's architecture, an adaptive frequency tracking & correcting algorithm and its FPGA implementation structure in real-time.

A notch filter includes an inductor coupled between an input node and an output node, and a dual-resonator structure coupled between the input node, the output node, and ground.