Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

A radio frequency identification (RFID) tag includes an antenna structure, a tank circuit, and a processing module that includes a tuning circuit. The processing module requires a processing module power level to operate according to a protocol. The tuning circuit requires a tuning circuit power level to adjust input impedance. The processing module power level is greater than the tuning circuit level. The processing module measures a first power level from a received RF signal. When the first power level is greater than the tuning circuit power level but less than the processing module power level, the processing module adjusts the input impedance to increase efficiency of power measurement and measures a second power level from the received RF signal. When and the second power level is greater than the processing module power level, the processing module uses the second power level to operate according to the protocol.

A radio frequency identification (RFID) tag includes an antenna structure, a tank circuit, and a processing module that includes a tuning circuit. The processing module requires a processing module power level to operate according to a protocol. The tuning circuit requires a tuning circuit power level to adjust input impedance. The processing module power level is greater than the tuning circuit level. The processing module measures a first power level from a received RF signal. When the first power level is greater than the tuning circuit power level but less than the processing module power level, the processing module adjusts the input impedance to increase efficiency of power measurement and measures a second power level from the received RF signal. When and the second power level is greater than the processing module power level, the processing module uses the second power level to operate according to the protocol.

Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

A capacitor bank has a capacitance value that is discontinuous and has an extremely narrow variable range. Thus, in a case of obtaining a wide variable range of the capacitance value, a large number of capacitors are connected in parallel and used while being switched by switches. The present technology achieves at least one of: allowing the capacitance value of a variable capacitance circuit to be varied continuously by electrical control without increasing the parasitic capacitance; and decreasing the current consumption of an oscillator circuit using the variable capacitance circuit as compared to a conventional case. The variable capacitance circuit includes: a transconductance circuit that includes a MOS transistor; an inductor that is connected in parallel to the transconductance circuit; and a Gm control circuit that varies a transconductance of the MOS transistor.

A method includes sending, by a reader, a radio frequency (RF) signal to a wireless sensor that includes an antenna having a tail section and a head section. The tail section is for placement in an RF limited area for sensing moisture in a first location of a vehicle under test and wherein the head section is for placement in a non-RF limited area. The method further includes receiving, by the reader, an RF response to the RF signal from the wireless sensor. The first RF response includes an indication of adjustment of one or more RF characteristics of the wireless sensor, which corresponds to a variance of the one or more RF characteristics from a desired value, which, in turn, corresponds to a level of moisture at the first location. The method further includes outputting, by the reader, a message regarding the level of moisture at the first location.

A method includes sending, by a reader, a radio frequency (RF) signal to a wireless sensor that includes an antenna having a tail section and a head section. The tail section is for placement in an RF limited area for sensing moisture in a first location of a vehicle under test and wherein the head section is for placement in a non-RF limited area. The method further includes receiving, by the reader, an RF response to the RF signal from the wireless sensor. The first RF response includes an indication of adjustment of one or more RF characteristics of the wireless sensor, which corresponds to a variance of the one or more RF characteristics from a desired value, which, in turn, corresponds to a level of moisture at the first location. The method further includes outputting, by the reader, a message regarding the level of moisture at the first location.

An electronic device is provided. The electronic device includes a first conductive layer, a second conductive layer that is formed to be opposite to the first conductive layer. The second conductive layer includes conductors that are electrically separated, and one or more photo-conductive members connected between the conductors. The electronic device further includes an insulating layer that is interposed between the first conductive layer and the second conductive layer, one or more light sources positioned to face the one or more photo-conductive members, and a control circuit. The control circuit outputs a specified light through the light source such that an electric conductivity of the photo-conductive member increases in response to a light, from among the photo-conductive members and some conductors are electrically connected with the photo-conductive member, and a capacitance value between the first conductive layer and the second conductive layer is changed.