A passive wireless temperature sensor includes a radio frequency (RF) front end having a variable input impedance. The RF front end includes an antenna operable to receive an RF signal having a particular carrier frequency and a tuning circuit having a resonant frequency corresponding to the particular carrier frequency. The passive wireless temperature sensor further includes one or more temperature sensing elements coupled to the RF front end. When sensing a temperature, the one or more temperature sensing elements cause a change in the variable input impedance. The passive wireless temperature sensor further includes a processing module operably coupled to the RF front end operable to adjust the resonant frequency of the tuning circuit to compensate for the change in the variable input impedance and generate a coded value representative of the change. The coded value representative of the change corresponds to the sensed temperature.

A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Biomedical implants in accordance with various embodiments of the invention can be implemented in many different ways. The implants can be configured to receive power and transmit data, both wirelessly and simultaneously. Such devices can be configured to receive power from an external source and transmit data, such as but not limited to recorded neural data and/or other biological data, to outside the body. In many cases, the data is transmitted to the device that delivers power to the implant. For example, the power and data transmission system can be implemented with a pair of transceivers. The implant transceiver can receive power wirelessly though an external transceiver while simultaneously transmitting data to the external transceiver. In several embodiments, both forward (power) and reverse (data) links use the same pair of inductive coils in the transceivers, one coil mounted in the implant and the other in the external unit.

Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

A capacitive wireless charging system for use with a vehicle includes a roadway-side capacitive charging pad configured to be embedded in a roadway and to form a capacitive electrical connection with a vehicle-side capacitive charging pad for wirelessly transferring power to charge a vehicle battery when the vehicle is on the roadway, a power conditioning circuit configured to be positioned next to the roadway and to condition power received from a power source, and a plurality of conductors configured to be at least partially embedded in the roadway and to electrically connect the power conditioning circuit and the roadway-side capacitive charging pad, such that the plurality of conductors form a roadway-side matching network for the capacitive electrical connection without discrete inductors and capacitors.

A capacitive wireless charging system for use with a vehicle includes a roadway-side capacitive charging pad configured to be embedded in a roadway and to form a capacitive electrical connection with a vehicle-side capacitive charging pad for wirelessly transferring power to charge a vehicle battery when the vehicle is on the roadway, a power conditioning circuit configured to be positioned next to the roadway and to condition power received from a power source, and a plurality of conductors configured to be at least partially embedded in the roadway and to electrically connect the power conditioning circuit and the roadway-side capacitive charging pad, such that the plurality of conductors form a roadway-side matching network for the capacitive electrical connection without discrete inductors and capacitors.

A low noise amplifier that may include a first input port, a second input port, a first capacitor, a second capacitor, a first variable capacitor, a second variable capacitor, an inductor, a bias circuit, a tuning circuit, a first output circuit having a first output, a second output circuit having a second output; wherein the first input port is electrically coupled to a first end of the second variable capacitor, to a first end of the first capacitor, to an input of the first output circuit, and to a first port of the inductor; wherein the second input port is electrically coupled to a second end of the first variable capacitor, to a second end of the second capacitor, to an input of the second output circuit, and to a second port of the inductor; wherein a first port of the first varactor is electrically coupled to a second end of the first capacitor; wherein a second port of the second varactor is electrically coupled to a first end of the second capacitor; wherein the bias circuit is configured to supply a bias voltage to a third port of the inductor; and wherein the tuning circuit is configured to control a capacitance of the first varactor and a capacitance of the variable capacitor.