A harmonic suppression system, including an interface connector is connected to a common end of a first differential SPMT switch; a control port of the first differential SPMT switch is connected to a control port of a second differential SPMT switch, and a gating throw end of the first differential SPMT switch is separately connected to one end of each LC trap network in a one-to-one correspondence; the control port of the second differential SPMT switch is connected to a baseband chip, each gating throw end of the second differential SPMT switch is separately connected to the other end of each LC trap network in a one-to-one correspondence, and a common end of the second differential SPMT switch is connected to the baseband chip; the baseband chip is connected to an antenna switch; and the antenna switch is connected to a antenna.

A system that incorporates the subject disclosure may include, for example, a circuit for determining a magnitude difference between a first signal supplied to an antenna and a second signal radiated by the antenna, determining a phase difference between the first signal supplied to the antenna and the second signal radiated by the antenna, measuring a change in reactance of an antenna, detecting an offset in an operating frequency of the antenna based on one of the magnitude difference, the phase difference, the change in reactance, or any combination thereof, and adjusting a resonant frequency of the antenna to mitigate the offset in the operating frequency of the antenna. Other embodiments are disclosed.

In accordance with an embodiment, a switchable capacitance circuit includes a plurality of capacitance-switch cells that each have a capacitance circuit having a capacitance between a first terminal and a second terminal of the capacitance circuit, and a semiconductor switching circuit including a first terminal coupled to the first terminal of the capacitance circuit, a plurality of series connected radio-frequency (RF) switch cells having a load path and a common node. Each of the plurality of series connected RF switch cells has a switch transistor and a gate resistor having a first end coupled to a gate of the switch transistor and a second end coupled to the common node. The switchable capacitance circuit also includes a resistance circuit having a first end coupled to the common node and a second end coupled to a control node.

A capacitive MEMS structure comprising first and second opposing capacitor electrode arrangements, wherein at least one of the electrode arrangements is movable, and a dielectric material located adjacent to the second electrode arrangement, wherein the second electrode arrangement is patterned such that it includes electrode areas and spaces adjacent to the electrode areas, and wherein the dielectric material extends at least partially in or over the spaces.

A device comprises a first capacitor block comprising a plurality of first capacitors connected in a first configuration, a second capacitor block comprising a plurality of second capacitors connected in the first configuration, a third capacitor block comprising a plurality of third capacitors connected in a second configuration, a fourth capacitor block comprising a plurality of fourth capacitors connected in the second configuration, a first switch connected between the first capacitor block and the second capacitor block, a second switch connected between the third capacitor block and the fourth capacitor block, a third switch connected between the first capacitor block and the fourth capacitor block and a fourth switch connected between the third capacitor block and the second capacitor block.

A Domino circuit for impedance tuning circuit can include a first node and a second node, and an inductance circuit including an inductor and a first switch connected in series such that the inductor is connected to the first node and the first switch is connected to the second node. The inductance circuit can further include a second switch implemented between ground and a third node between the inductor and the first switch, such that the inductance circuit is capable of providing a series inductance path between the first and second nodes or a shunt inductance path between the third node and the ground.