A radio-frequency impedance tuner can include first and second nodes, a bypass path, first and second series capacitance paths, and an inductance path, with each path being implemented between the first and second nodes and including a switch configured to allow the path to couple or uncouple the first and second nodes. The tuner can further include first and second shunt paths, with each shunt path being implemented between the second node and ground and including a switch configured to allow the shunt path to couple or uncouple the second node and the ground. The tuner can further include a switchable grounding path implemented along the inductance path and configured to allow the inductance path to function as a series inductance path between the first and second nodes, or as a shunt inductance path between the ground and a node along the inductance path.

Biomedical implants in accordance with various embodiments of the invention can be implemented in many different ways. The implants can be configured to receive power and transmit data, both wirelessly and simultaneously. Such devices can be configured to receive power from an external source and transmit data, such as but not limited to recorded neural data and/or other biological data, to outside the body. In many cases, the data is transmitted to the device that delivers power to the implant. For example, the power and data transmission system can be implemented with a pair of transceivers. The implant transceiver can receive power wirelessly though an external transceiver while simultaneously transmitting data to the external transceiver. In several embodiments, both forward (power) and reverse (data) links use the same pair of inductive coils in the transceivers, one coil mounted in the implant and the other in the external unit.

A capless impedance tuner can include first node and second nodes, a first series path, a second series path, and an inductance path, each between the first node and the second node and including a switch to allow the path to couple or uncouple the first and second nodes. Each series path can be configured to allow a substantially continuous flow of a direct current between the first node and the second node when coupled. The tuner can further include a shunt path with a switch to allow coupling or uncoupling of the second node and ground. The tuner can further include a switchable grounding path implemented along the inductance path and configured to allow the inductance path to function as a series inductance path between the first and second nodes, or as a shunt inductance path between the ground and a node along the inductance path.

A capless impedance tuner can include first node and second nodes, a first series path, a second series path, and an inductance path, each between the first node and the second node and including a switch to allow the path to couple or uncouple the first and second nodes. Each series path can be configured to allow a substantially continuous flow of a direct current between the first node and the second node when coupled. The tuner can further include a shunt path with a switch to allow coupling or uncoupling of the second node and ground. The tuner can further include a switchable grounding path implemented along the inductance path and configured to allow the inductance path to function as a series inductance path between the first and second nodes, or as a shunt inductance path between the ground and a node along the inductance path.

A multiport RF switch assembly with integrated impedance tuning capability is described that provides a single RFIC solution to switch between transmit and receive paths in a communication system. Dynamic tuning is integrated into each switch sub-assembly to provide the capability to impedance match antennas or other components connected to the multiport switch. The tuning function at the switch can be used to shape the antenna response to provide better filtering at the switch/RF front-end (RFFE) interface to allow for reduced filtering requirements in the RFFE. Memory is designed into the multiport switch assembly, allowing for a look-up table or other data to reside with the switch and tuning circuit. The resident memory will result in easier integration of the tunable switch assembly into communication systems.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

An oscillator includes a tunable resonant circuit having an inductance and a variable capacitance coupled between first and second nodes, and a set of capacitances selectively coupleable between the first and second nodes. An input control node receiving an input control signal is coupled to the variable capacitance and set of capacitances. The tunable resonant circuit is tunable based on the input control signal. A biasing circuit biases the tunable resonant circuit to generate a variable-frequency output signal between the first and second nodes. A voltage divider generates a set of different voltage thresholds, and a set of comparator circuits with hysteresis compares the input control signal to the set of different voltage thresholds to generate a set of control signals. The capacitances in the set of capacitances are selectively coupleable between the first and second nodes as a function of control signals in the set of control signals.

In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.

In one embodiment, a phase detection circuit includes a current signal input to receive a current signal indicative of a current amplitude of an RF signal and a voltage signal input to receive a voltage signal indicative of a voltage amplitude of the RF signal. A high-pass filter and a low-pass filter are each configured to filter one of (i) the current signal from the current signal input or (ii) the voltage signal from the voltage signal input, wherein the high-pass filter and the low-pass filter collectively cause a substantially 90 degree offset between a phase angle of the current signal and a phase angle of the voltage signal. A phase difference circuit receives the filtered current signal and the filtered voltage signal to determine a phase angle difference between the current signal and the voltage signal.