In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

A biasing circuit for biasing a switching transistor, wherein the switching transistor is used for switching a respective capacitor cell into/out of a capacitor array, wherein the capacitor array comprises one or more such capacitor cells, and wherein the capacitor array is coupled in parallel with a primary inductor to form an inductive/capacitive tank. The biasing circuit comprises a secondary inductor which is inductively coupled to the primary inductor, the secondary inductor configured to provide a bias signal for biasing the switching transistor.

A method couples a first bias signal to first and second internal nodes via first and second resistors, couples a second bias signal to third and fourth internal nodes via third and fourth resistors, couples the first internal node to the second internal node via a switch of a first type, and couples the third internal node to the fourth internal node via a switch of a second type. The method further couples the first internal node to the third internal node via a first transmission gate, couples the second internal node to the fourth internal node via a second transmission gate, couples a first terminal to the first and third internal nodes via first and third capacitors, respectively, and couples a second terminal to the second and fourth internal nodes via second and fourth capacitors, respectively.

Embodiments of the present disclosure include a microcontroller with a frequency test circuit, a device-under-test (DUT) input, and a calculation engine circuit. The calculation engine circuit is configured to compare a measured frequency from the frequency test circuit measured from the DUT input to a reference frequency stored in memory, and, based on the comparison, adjust frequency of the DUT generating the DUT input.

A method includes sending, by a reader, a radio frequency (RF) signal to a wireless sensor that includes an antenna having a tail section and a head section. The tail section is for placement in an RF limited area for sensing moisture in a first location of a vehicle under test and wherein the head section is for placement in a non-RF limited area. The method further includes receiving, by the reader, an RF response to the RF signal from the wireless sensor. The first RF response includes an indication of adjustment of one or more RF characteristics of the wireless sensor, which corresponds to a variance of the one or more RF characteristics from a desired value, which, in turn, corresponds to a level of moisture at the first location. The method further includes outputting, by the reader, a message regarding the level of moisture at the first location.

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Embodiments of resonator circuits and modulating resonators and are described generally herein. One or more acoustic wave resonators may be coupled in series or parallel to generate tunable filters. One or more acoustic wave resonances may be modulated by one or more capacitors or tunable capacitors. One or more acoustic wave modules may also be switchable in a filter. Other embodiments may be described and claimed.

A power detector for use in an RF receiver. The detector includes a power reference generator and a power quantizer. The power reference generator develops a power reference current, voltage, or signal as a function of a power transferred via a received RF signal. The power quantizer is responsive to the power reference current, voltage, or signal to develop a digital field power value indicative of the power reference current, voltage, or signal.

A power detector for use in an RF receiver. The detector includes a power reference generator and a power quantizer. The power reference generator develops a power reference current, voltage, or signal as a function of a power transferred via a received RF signal. The power quantizer is responsive to the power reference current, voltage, or signal to develop a digital field power value indicative of the power reference current, voltage, or signal.

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.