The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

A circuit device includes an oscillation signal generation circuit for generating an oscillation signal with an oscillation frequency set by frequency control data, and a processing circuit. The processing circuit includes a counter for performing a count process based on the oscillation signal, and a latch circuit for holding a count value of the counter based on a reference signal. The processing circuit performs a loop filter process on a phase comparison result based on output data of the latch circuit to output the frequency control data, holds information based on the phase comparison result when the holdover is detected, and outputs the frequency control data based on the information held, in a holdover period.

A method for operating a clock product includes generating a quality determination for a reference clock signal based on frequency metrics for a plurality of independent clock signals. The frequency metrics are generated using the reference clock signal. The method includes generating an output clock signal by locking to an active clock signal selected from the plurality of independent clock signals in response to the quality determination satisfying a predetermined quality metric. For each input clock signal of the plurality of independent clock signals, the frequency metrics include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts, and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.

A signal phase aligning system includes a signal generator configured to generate a signal. The system further includes a phase locked loop circuit configured to generate a phase locked loop signal based on the signal generated by the signal generator. The system includes a phase aligning circuit configured to align a phase of the phase locked loop signal with a phase of the signal generated by the signal generator.

Various communication systems may benefit from improved user equipment bandwidth allocation. For example, it may be helpful to improve user equipment bandwidth part switching for uplink transmissions. A method may include determining at a user equipment a need for retuning a radio frequency based on a received downlink transmission bandwidth. The method may also include determining at the user equipment a time for the retuning of the radio frequency. In addition, the method may include retuning at the user equipment the radio frequency at the determined time. Further, the method may include transmitting data from the user equipment to a network entity using the retuned radio frequency.

A method and apparatus for utilizing a wideband radio frequency filter to capture an FM frequency band and configuring the characteristics of a delta-sigma modulator in order to processes desired signals within the FM frequency band. Specifically, the system and method are operative to receive a plurality of FM signals within an FM frequency band, filter the frequency band using a wideband filter, modulating the plurality of FM signals using a delta sigma modulator, down converting and processing the desired signals in parallel.

A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

An electronic device may include an adjustable power supply, at least one antenna, and associated antenna tuning circuitry. The antenna tuning circuitry may be an integral part of the antenna and may include a control circuit and at least one tunable element. The tunable element may include radio-frequency switches, continuously/semi-continuously adjustable components such as tunable resistors, inductors, and capacitors, and other load circuits that provide desired impedance characteristics. The power supply may provide power supply voltage signals to the antenna tuning circuitry via inductive coupling. The power supply voltage signals may be modulated according to a predetermined lookup table during device startup so that the control circuit is configured to generate desired control signals. These control signals adjust the tunable element so that the antenna can support wireless operation in desired frequency bands.