A circuit and method are provided. The method couples a first bias signal to a first internal node and a second internal node via a first resistor and a second resistor, respectively, couples a second bias signal to a third internal node and a fourth internal node via a third resistor and a fourth resistor, respectively. The method further couples the first internal node to the second internal node via a switch of a first type controlled by a first control signal, couples the third internal node to the fourth internal node via a switch of a second type controlled by a second control signal, wherein the second control signal is an inversion of the first control signal, couples a first terminal to the first internal node and the third internal node via a first capacitor and a third capacitor, respectively; and couples a second terminal to the second internal node and the fourth internal node via a second capacitor and a fourth capacitor, respectively.

A circuit and method are provided. The method couples a first bias signal to a first internal node and a second internal node via a first resistor and a second resistor, respectively, couples a second bias signal to a third internal node and a fourth internal node via a third resistor and a fourth resistor, respectively. The method further couples the first internal node to the second internal node via a switch of a first type controlled by a first control signal, couples the third internal node to the fourth internal node via a switch of a second type controlled by a second control signal, wherein the second control signal is an inversion of the first control signal, couples a first terminal to the first internal node and the third internal node via a first capacitor and a third capacitor, respectively; and couples a second terminal to the second internal node and the fourth internal node via a second capacitor and a fourth capacitor, respectively.

Portable high-voltage electrical stimulation devices and systems are disclosed that are scalable to utilize a minimal number of output channels to a large number of output channels. The devices and systems include a high-voltage power supply and output pulse circuitry comprising a plurality of output channel circuits. The electrical stimulation devices and systems disclosed herein also provide improved safety features, including an optional safety monitor.

Portable high-voltage electrical stimulation devices and systems are disclosed that are scalable to utilize a minimal number of output channels to a large number of output channels. The devices and systems include a high-voltage power supply and output pulse circuitry comprising a plurality of output channel circuits. The electrical stimulation devices and systems disclosed herein also provide improved safety features, including an optional safety monitor.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.

Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.

A window type watchdog timer includes a frequency dividing circuit for generating a frequency-divided clock signal by dividing a frequency of a reference clock signal; a monitoring circuit for monitoring occurrence of a first error in which clear control from a target device is interrupted for a first time or more, and occurrence of a second error in which an interval between two consecutive clear controls from the target device is shorter than a second time shorter than the first time, based on the frequency-divided clock signal; and outputting an error signal when the first error or the second error is detected; and a setting circuit for variably setting the first time and the second time by variably setting a frequency division ratio in the frequency dividing circuit and variably setting a detection condition of the first error and the second error.

A window type watchdog timer includes a frequency dividing circuit for generating a frequency-divided clock signal by dividing a frequency of a reference clock signal; a monitoring circuit for monitoring occurrence of a first error in which clear control from a target device is interrupted for a first time or more, and occurrence of a second error in which an interval between two consecutive clear controls from the target device is shorter than a second time shorter than the first time, based on the frequency-divided clock signal; and outputting an error signal when the first error or the second error is detected; and a setting circuit for variably setting the first time and the second time by variably setting a frequency division ratio in the frequency dividing circuit and variably setting a detection condition of the first error and the second error.