A method of operating an inverter including the steps of detecting the temperature of the at least one electrolytic capacitor; selecting at least one of a plurality of switching patterns based on the temperature of the at least one electrolytic capacitor; and generating a ripple current across the at least one electrolytic capacitor by operating the inverter from the at least one of the plurality of switching patterns for preheating of the at least one electrolytic capacitor.

A method of operating an inverter including the steps of detecting the temperature of the at least one electrolytic capacitor; selecting at least one of a plurality of switching patterns based on the temperature of the at least one electrolytic capacitor; and generating a ripple current across the at least one electrolytic capacitor by operating the inverter from the at least one of the plurality of switching patterns for preheating of the at least one electrolytic capacitor.

An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

A highly reliable semiconductor device in which a shift in threshold voltage of a transistor due to deterioration can be inhibited is provided. A pulse output circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. A clock signal is supplied to a drain of the first transistor. A first power supply potential is applied to a source of the second transistor, and a drain of the second transistor is connected to the drain of the first transistor. A second power supply potential is applied to a drain of the third transistor. The first power supply potential is applied to a source of the fourth transistor, and a drain of the fourth transistor is connected to the drain of the third transistor. The first power supply potential is applied to a source of the fifth transistor, and a drain of the fifth transistor is connected to a gate of the third transistor. One of a source and a drain of the sixth transistor is connected to the drain of the first transistor, and the other of the source and the drain of the sixth transistor is connected to the gate of the third transistor. The first transistor and the third transistor include back gates connected to each other. The first to sixth transistors have the same conductivity type.

A highly reliable semiconductor device in which a shift in threshold voltage of a transistor due to deterioration can be inhibited is provided. A pulse output circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. A clock signal is supplied to a drain of the first transistor. A first power supply potential is applied to a source of the second transistor, and a drain of the second transistor is connected to the drain of the first transistor. A second power supply potential is applied to a drain of the third transistor. The first power supply potential is applied to a source of the fourth transistor, and a drain of the fourth transistor is connected to the drain of the third transistor. The first power supply potential is applied to a source of the fifth transistor, and a drain of the fifth transistor is connected to a gate of the third transistor. One of a source and a drain of the sixth transistor is connected to the drain of the first transistor, and the other of the source and the drain of the sixth transistor is connected to the gate of the third transistor. The first transistor and the third transistor include back gates connected to each other. The first to sixth transistors have the same conductivity type.

A voltage clamp circuit which operates using a voltage controlled current source where the change of the polarity of the voltage controlled current source controls whether it is clamping or not. While clamping, the stability of the control loop uses the capacitance of the output to create and single pole roll-off of the loop gain and while not clamping, uses the capacitance of the circuit which sets the clamping voltage to produce the roll-off. The circuit operates in a linear fashion both while clamping and not clamping, which allows for a faster response when clamping is needed.

A voltage clamp circuit which operates using a voltage controlled current source where the change of the polarity of the voltage controlled current source controls whether it is clamping or not. While clamping, the stability of the control loop uses the capacitance of the output to create and single pole roll-off of the loop gain and while not clamping, uses the capacitance of the circuit which sets the clamping voltage to produce the roll-off. The circuit operates in a linear fashion both while clamping and not clamping, which allows for a faster response when clamping is needed.

A window type watchdog timer includes a frequency dividing circuit for generating a frequency-divided clock signal by dividing a frequency of a reference clock signal; a monitoring circuit for monitoring occurrence of a first error in which clear control from a target device is interrupted for a first time or more, and occurrence of a second error in which an interval between two consecutive clear controls from the target device is shorter than a second time shorter than the first time, based on the frequency-divided clock signal; and outputting an error signal when the first error or the second error is detected; and a setting circuit for variably setting the first time and the second time by variably setting a frequency division ratio in the frequency dividing circuit and variably setting a detection condition of the first error and the second error.

A window type watchdog timer includes a frequency dividing circuit for generating a frequency-divided clock signal by dividing a frequency of a reference clock signal; a monitoring circuit for monitoring occurrence of a first error in which clear control from a target device is interrupted for a first time or more, and occurrence of a second error in which an interval between two consecutive clear controls from the target device is shorter than a second time shorter than the first time, based on the frequency-divided clock signal; and outputting an error signal when the first error or the second error is detected; and a setting circuit for variably setting the first time and the second time by variably setting a frequency division ratio in the frequency dividing circuit and variably setting a detection condition of the first error and the second error.