Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.

Disclosed is a resonant circuit and method for matched clock and data timing performance for improving timing closure of digital circuits on advanced semiconductor manufacturing processes. The matched resonance circuit comprises pulse generator circuit (202) and plurality of generating latches (206A-N) and plurality of sampling latches (304A-N). The pulse generator circuit (202) comprises plurality of inverters (210A-N), optimum resistance (214) and exclusive OR (Ex-OR) gate (218) which are connected in series and a matched capacitance. The pulse generator circuit (202) generates timing pulse output using one or more buffers and clock inductor. Each generating latch receives clock timing pulse output as timing pulse into plurality of sampling flip-flop latches (304A-N) through clock sample path (CS) to match arrival of timing pulse and outputs of plurality of input data lines that are resonated by connecting one or more of respective load capacitances with at least one shared inductor (208).

In a power switching apparatus, a first switch includes a first end coupled to a first input terminal, a second end coupled to an output terminal, and a control end coupled to a second input terminal and coupled to a ground via a first resistor. A second resistor is coupled between the output terminal and the ground. A second switch includes a first end coupled to the second input terminal, a second end coupled to the output terminal and a control end coupled to the ground via a third resistor. A third switch includes a first end coupled to the control end of the second switch and the first end of the third resistor, a second end coupled to the first input terminal and a control end coupled to the second input terminal and coupled to the ground via the first resistor.

In a power switching apparatus, a first switch includes a first end coupled to a first input terminal, a second end coupled to an output terminal, and a control end coupled to a second input terminal and coupled to a ground via a first resistor. A second resistor is coupled between the output terminal and the ground. A second switch includes a first end coupled to the second input terminal, a second end coupled to the output terminal and a control end coupled to the ground via a third resistor. A third switch includes a first end coupled to the control end of the second switch and the first end of the third resistor, a second end coupled to the first input terminal and a control end coupled to the second input terminal and coupled to the ground via the first resistor.

Various embodiments of the present technology comprise a method and apparatus for a current circuit. According to various embodiments, the current circuit may be utilized for current detection or current limiting. The current circuit may be configured to compensate for a base current, making detection of an input current more accurate.

Various embodiments of the present technology comprise a method and apparatus for a current circuit. According to various embodiments, the current circuit may be utilized for current detection or current limiting. The current circuit may be configured to compensate for a base current, making detection of an input current more accurate.

An embodiment device comprises a processing circuit and IP circuitry coupled to a power supply line, wherein the IP circuitry has an IP circuitry supply threshold for IP circuitry operation. A supply monitor circuit is coupled to the power supply line to sense the voltage on the power supply line and to switch the processing circuit to a low-power mode as a result of a drop in the voltage on the power supply line. The supply monitor circuit comprises a threshold setting node and is configured to be deactivated as a result of the voltage on the power supply line dropping below a deactivation threshold level set at the threshold setting node. A threshold setting circuit is configured to apply to the threshold setting node of the supply monitor circuit the IP circuitry supply threshold as a result of the processing circuit being in the low-power mode.

An embodiment device comprises a processing circuit and IP circuitry coupled to a power supply line, wherein the IP circuitry has an IP circuitry supply threshold for IP circuitry operation. A supply monitor circuit is coupled to the power supply line to sense the voltage on the power supply line and to switch the processing circuit to a low-power mode as a result of a drop in the voltage on the power supply line. The supply monitor circuit comprises a threshold setting node and is configured to be deactivated as a result of the voltage on the power supply line dropping below a deactivation threshold level set at the threshold setting node. A threshold setting circuit is configured to apply to the threshold setting node of the supply monitor circuit the IP circuitry supply threshold as a result of the processing circuit being in the low-power mode.

An output driving system includes an output driver, a first ESD (Electrostatic Discharge) protection circuit, a second ESD protection circuit, a first differential amplifier, a second differential amplifier, a first capacitor, and a second capacitor. The output driver has a first output node for outputting a first output voltage, and a second output node for outputting a second output voltage. The first differential amplifier generates a first amplified voltage according to the first output voltage and the second output voltage. The first capacitor has a first terminal for receiving the first amplified voltage, and a second terminal coupled to the first output node. The second differential amplifier generates a second amplified voltage according to the first output voltage and the second output voltage. The second capacitor has a first terminal for receiving the second amplified voltage, and a second terminal coupled to the second output node.

In a power switching apparatus, a first switch includes a first end coupled to a first input terminal, a second end coupled to an output terminal, and a control end coupled to a second input terminal and coupled to a ground via a first resistor. A second resistor is coupled between the output terminal and the ground. A second switch includes a first end coupled to the second input terminal, a second end coupled to the output terminal and a control end coupled to the ground via a third resistor. A third switch includes a first end coupled to the control end of the second switch and the first end of the third resistor, a second end coupled to the first input terminal and a control end coupled to the second input terminal and coupled to the ground via the first resistor.