A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A signal generating system is provided. The signal generating system provides a microwave signal to a plurality of qubits. The signal generating system includes a generator, an oscillator, a mixer, and a splitter. The oscillator generates an oscillator signal including a constant frequency. The generator generates a generator signal including an initial frequency. The mixer is electrically coupled to the generator and the oscillator. The mixer combines the generator and oscillator signals to produce the microwave signal. The splitter is electrically coupled to the mixer. The splitter fans-out the microwave signal to a plurality of physical lines. Each of the plurality of physical lines is electrically connected to a corresponding one of the plurality of qubits.

Disclosed are a phase-tracked pulse generation circuit and a power supply device. The present application uses a driving pulse rising edge of a power supply as a reference, and uses a constant current circuit to charge a charging and discharging circuit at a constant current. When the reference driving pulse rising edge comes, the charging and discharging circuit is discharged; the peak voltage on the charging and discharging circuit is taken out and then divided for comparison with the voltage on the charging and discharging circuit; when the voltage on the charging and discharging circuit is equal to a divided voltage value of the peak voltage, the output of a comparison circuit turns high, and the output of a comparator is the phase-tracked pulse; the rising edge of the phase-tracked pulse can be used for synchronizing another power supply.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

Methods and devices for generating a voltage waveform at an output may include providing four DC voltages of different magnitudes. The first (V.sub.1) magnitude is higher than the third (V.sub.3) and fourth (V.sub.4) magnitude. The fourth DC voltage is coupled to the output followed by coupling the first DC voltage to the output, to bring an output voltage (V.sub.P) at the output to a high level. The first DC voltage is decoupled from the output, followed by coupling the third DC voltage to the output, to obtain a drop of the output voltage (V.sub.P). A ground potential (V.sub.0) is coupled to the output following coupling the third DC voltage and the second DC current (I.sub.2) is coupled to the output following coupling the ground potential, wherein the second DC current ramps down the output voltage (V.sub.P).

A comb signal generator that includes at least two signal sources that each provide a signal, wherein the signals provided by the at least two signal sources are shaped similarly. The comb signal generator also has a combining circuit connected with the at least two signal sources, wherein the combining circuit is configured to combine the signals provided by the at least two signal sources, thereby generating a combined signal. Further, the comb signal generator includes a clipping circuit connected with the combining circuit, wherein the clipping circuit is configured to receive and process the combined signal, thereby generating a comb signal. Further, a method of providing a phase and amplitude reference is described.