Random number generator (GL) comprising adjustable speed ring oscillators (GPRS, GPRS′), which have outputs (o-GPRS, o-GPRS′) connected to inputs (i1-UM, i2-UM) of a metastability circuit (UM) and inputs (i1-DF, i2-DF) of a phase detector (DF), which outputs (o-UM, o-DF) are connected to inputs (r-US′, i-US′) of a control circuit (US′), having output (o-US′) connected to control inputs (s-GPRS, s-GPRS′) of the adjustable speed ring oscillators (GPRS, GPRS′). The outputs (o-UM, o-DF) of the metastability circuit (UM) and the phase detector (DF) are being outputs (o-GL, o2-GL) of the random number generator (GL).

The present description concerns an integrated circuit including, between first and second terminals having a first voltage applied therebetween, a load configured to execute instructions, a circuit for delivering a digital signal having at least two bits from a binary signal and a current output digital-to-analog converter controlled by the digital signal and coupled between the first and second terminals in parallel with the load.

The present description concerns an integrated circuit including, between first and second terminals having a first voltage applied therebetween, a load configured to execute instructions, a circuit for delivering a digital signal having at least two bits from a binary signal and a current output digital-to-analog converter controlled by the digital signal and coupled between the first and second terminals in parallel with the load.

Disclosed herein is an apparatus that includes a first circuit configured to generate a first signal a first number of times in response to an input signal, a second circuit configured to generate a second signal having a second numerical value each time the first signal is activated, and a third circuit configured to receive the second signal to update a count value obtained by accumulating the second numerical value, configured to generate a third signal each time the count value reaches a third numerical value, and configured to update the count value obtained by accumulating the second numerical value and subtracting the third numerical value when the count value reached the third numerical value.

Disclosed herein is an apparatus that includes a first circuit configured to generate a first signal a first number of times in response to an input signal, a second circuit configured to generate a second signal having a second numerical value each time the first signal is activated, and a third circuit configured to receive the second signal to update a count value obtained by accumulating the second numerical value, configured to generate a third signal each time the count value reaches a third numerical value, and configured to update the count value obtained by accumulating the second numerical value and subtracting the third numerical value when the count value reached the third numerical value.

A random number generator that includes control circuit, an oscillation circuit, a dynamic header circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The dynamic header circuit generates a bias voltage based on the configuration of the bias control signal. The oscillation circuit generates an oscillation signal based on the bias voltage. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

A random number generator that includes control circuit, an oscillation circuit, a dynamic header circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The dynamic header circuit generates a bias voltage based on the configuration of the bias control signal. The oscillation circuit generates an oscillation signal based on the bias voltage. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

A system for generating a biased random bit stream, wherein said biased bit stream has different predetermined probabilities of occurrence for bit “0” and bit “1”, said system comprising: a true random generator unit configured to output a true random bit stream, a pseudo random generator unit configured to output a pseudo random bit stream, said pseudo random bit stream comprising n bit words, where n is an integer of at least two; a combining unit configured to combine a bit from said true random generator unit with an n-bit word from said pseudo random generator unit to output a processed n-bit word; and an output unit configured to generate an output bit value from said processed n-bit word using a function, wherein said function is selected to control the probabilities of occurrence of the bit “0” values and bit “1” values to be the predetermined probabilities of occurrence.

A system for generating a biased random bit stream, wherein said biased bit stream has different predetermined probabilities of occurrence for bit “0” and bit “1”, said system comprising: a true random generator unit configured to output a true random bit stream, a pseudo random generator unit configured to output a pseudo random bit stream, said pseudo random bit stream comprising n bit words, where n is an integer of at least two; a combining unit configured to combine a bit from said true random generator unit with an n-bit word from said pseudo random generator unit to output a processed n-bit word; and an output unit configured to generate an output bit value from said processed n-bit word using a function, wherein said function is selected to control the probabilities of occurrence of the bit “0” values and bit “1” values to be the predetermined probabilities of occurrence.

The semiconductor device comprises a first ring oscillator and a second ring oscillator. An input of the first ring oscillator is an end output of the first ring oscillator and an output of the second ring oscillator and wherein an input of the second ring oscillator is an end output of the second ring oscillator and an output of the first ring oscillator.