Patent classifications
H03K3/84
Random number generator using cross-coupled ring oscillators
The semiconductor device comprises a first ring oscillator and a second ring oscillator. An input of the first ring oscillator is an end output of the first ring oscillator and an output of the second ring oscillator and wherein an input of the second ring oscillator is an end output of the second ring oscillator and an output of the first ring oscillator.
DATA PROCESSING DEVICE AND METHOD FOR OPERATING A DATA PROCESSING DEVICE
A method for ascertaining a randomized digital data stream. The method includes ascertaining a first bit stream as a function of an analog input data stream; ascertaining a second randomized bit stream as a function of the first bit stream, the second randomized bit stream being ascertained in a non-periodic temporal sequence; ascertaining a first digital data stream as a function of the second randomized bit stream; ascertaining a second digital data stream including pseudo random numbers; and ascertaining the randomized digital data stream as a function of the first digital data stream and as a function of the second digital data stream.
DATA PROCESSING DEVICE AND METHOD FOR OPERATING A DATA PROCESSING DEVICE
A method for ascertaining a randomized digital data stream. The method includes ascertaining a first bit stream as a function of an analog input data stream; ascertaining a second randomized bit stream as a function of the first bit stream, the second randomized bit stream being ascertained in a non-periodic temporal sequence; ascertaining a first digital data stream as a function of the second randomized bit stream; ascertaining a second digital data stream including pseudo random numbers; and ascertaining the randomized digital data stream as a function of the first digital data stream and as a function of the second digital data stream.
TRUE RANDOM NUMBER GENERATOR
The invention relates to devices for generating true random numbers, comprising a digital chaotically oscillating autonomous Boolean network as a source of entropy. According to the invention, the proposed digital chaotically oscillating autonomous Boolean network consists in three logic elements connected to each other, two of which represent two-input “Exclusive OR” and/or “Exclusive NOR” gates, and the third logic element has three inputs and one output, and implements a logic “counting ones” function, in which its output is set to a logic one if a logic one is present at no more than one of its inputs, otherwise it is set to a logic zero. The achieved technical result consists in an increase in true random number generation rate while decreasing energy consumption.
TRUE RANDOM NUMBER GENERATOR
The invention relates to devices for generating true random numbers, comprising a digital chaotically oscillating autonomous Boolean network as a source of entropy. According to the invention, the proposed digital chaotically oscillating autonomous Boolean network consists in three logic elements connected to each other, two of which represent two-input “Exclusive OR” and/or “Exclusive NOR” gates, and the third logic element has three inputs and one output, and implements a logic “counting ones” function, in which its output is set to a logic one if a logic one is present at no more than one of its inputs, otherwise it is set to a logic zero. The achieved technical result consists in an increase in true random number generation rate while decreasing energy consumption.
SYSTEM AND METHOD OF GENERATING QUANTUM UNITARY NOISE USING SILICON BASED QUANTUM DOT ARRAYS
A novel and useful system and method of generating quantum unitary noise using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0> and |1>. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. A detector circuit connected to the device outputs a digital stream corresponding to the probability of a particle of being detected. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability. The unitary noise can be used in stochastic rounding by controlling the bias applied to the barrier in accordance with a remainder of numbers to be rounded.
SYSTEM AND METHOD OF GENERATING QUANTUM UNITARY NOISE USING SILICON BASED QUANTUM DOT ARRAYS
A novel and useful system and method of generating quantum unitary noise using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0> and |1>. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. A detector circuit connected to the device outputs a digital stream corresponding to the probability of a particle of being detected. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability. The unitary noise can be used in stochastic rounding by controlling the bias applied to the barrier in accordance with a remainder of numbers to be rounded.
Information redistribution to reduce side channel leakage
A logic circuit includes a data signal input, a computational module, a direct timing modulator and an amplitude and non-direct timing modulator. The data signal input inputs data signals. The computational module includes multiple logic elements interconnected to perform a logic function. The direct timing modulator modulates a propagation time of the input data signals from the data signal input to the computational unit, in accordance with a first set of control signals. The amplitude and non-direct timing modulator modulates the processing time of data signals by the computational module and the amplitude of data signals propagating through the computational module, in accordance with a second set of control signals.
RANDOM NUMBER GENERATOR
An apparatus includes a ring oscillator, a carry chain circuit, and a detector circuit. The ring oscillator produces a clock signal. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates the clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.
RANDOM NUMBER GENERATOR
An apparatus includes a ring oscillator, a carry chain circuit, and a detector circuit. The ring oscillator produces a clock signal. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates the clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.