An electromagnetic interference reducing circuit is provided. A first random number generator generates a plurality of first random number signals each having a plurality of triangular waves. Each of the triangular waves has a plurality of steps. The first random number generator generates a plurality of first random numbers and modulates each of the first random number signals according to the first random numbers. The first random number generator repeatedly counts, repeatedly removes, or does not count time of the steps of each of the triangular waves of each of the first random number signals according to one of the first random numbers. A first oscillator generates a first oscillating signal. A motor controller circuit controls a plurality of switch components of a motor respectively according to the first random number signals based on the first oscillating signal.

An apparatus includes a ring oscillator, a carry chain circuit, and a detector circuit. The ring oscillator produces a clock signal. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates the clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.

An apparatus includes a ring oscillator, a carry chain circuit, and a detector circuit. The ring oscillator produces a clock signal. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates the clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.

A multi-frequency uniformization carrier wave slope random distribution pulse width modulation method, includes: (1) selecting a required random carrier wave sequence and a modulating wave, and after the two are compared, generating a switch device drive signal for pulse width modulation; (2) determining a multiple n of an equivalent carrier frequency f of the random carrier wave sequence, and selecting a main circuit topology; and (3) inputting the switch device drive signal generated in (1) into the main circuit topology of (2) to perform multi-frequency uniformization carrier wave slope random distribution pulse width modulation. The disclosure can improve a frequency domain distribution bandwidth of a harmonic wave without changing the mean and variance of a random carrier wave sequence, and realizes uniform distribution of carrier waves and multiple harmonic peaks near a doubled frequency of the carrier waves in a wider frequency domain.

A multi-frequency uniformization carrier wave slope random distribution pulse width modulation method, includes: (1) selecting a required random carrier wave sequence and a modulating wave, and after the two are compared, generating a switch device drive signal for pulse width modulation; (2) determining a multiple n of an equivalent carrier frequency f of the random carrier wave sequence, and selecting a main circuit topology; and (3) inputting the switch device drive signal generated in (1) into the main circuit topology of (2) to perform multi-frequency uniformization carrier wave slope random distribution pulse width modulation. The disclosure can improve a frequency domain distribution bandwidth of a harmonic wave without changing the mean and variance of a random carrier wave sequence, and realizes uniform distribution of carrier waves and multiple harmonic peaks near a doubled frequency of the carrier waves in a wider frequency domain.

Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits having a defined number of bits, where the sequence of bits represent a desired continuous pulse signal having a programmable width in time-domain. The apparatus can also can receive a precursor continuous pulse signal having an arbitrary width in time-domain that fits within the dynamic range of the apparatus. The apparatus can generate the desired continuous pulse signal by transforming the precursor continuous pulse signal using the sequence of bits and an inverse chaotic map.

A propagation delay balance circuit includes a signal generating circuit, a path switching element, and a signal change detecting element. The signal generating circuit includes delay chains for outputting delay signals respectively. The path switching element has input terminals and output terminals. Each output terminal of the path switching element is electrically connected to the input terminal of each delay chain one-to-one, and input terminals of the path switching element are electrically connected one-to-one to the output terminals of the delay chains. The path switching element is controlled by the path switching controlling signal to change the one-to-one internal electrical connection between input terminals and output terminals of the path switching element. The signal change detecting element is electrically connected to the path switching element, and generates a path switching controlling signal according to delay signals of the path switching element.

A propagation delay balance circuit includes a signal generating circuit, a path switching element, and a signal change detecting element. The signal generating circuit includes delay chains for outputting delay signals respectively. The path switching element has input terminals and output terminals. Each output terminal of the path switching element is electrically connected to the input terminal of each delay chain one-to-one, and input terminals of the path switching element are electrically connected one-to-one to the output terminals of the delay chains. The path switching element is controlled by the path switching controlling signal to change the one-to-one internal electrical connection between input terminals and output terminals of the path switching element. The signal change detecting element is electrically connected to the path switching element, and generates a path switching controlling signal according to delay signals of the path switching element.

An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.

An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.