An example embodiment includes an n-bit parallel pseudo-random binary sequence (PRBS) generator coupled to channelization circuitry to control the channelization circuitry to select from among a single channel n-bit output pattern from the PRBS generator and a number of multiple channel output patterns from the PRBS generator. The number of multiple channel output patterns can correspond to respective sub-patterns of the single channel n-bit output pattern.

A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.

A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.

A pseudo-random sequence generator for use within a universal lidar system and its corresponding method of operation. The pseudo-random sequence generator uses synchronized shift registers that are in series Binary adders are provided. The signal output of each of the shift registers is tapped and directed to the binary adders. High-speed switches are provided between the shift registers and the binary adders. The switches are programmed to connect only two of the shift registers to the binary adders for each of the pseudo-random patterns being generated. The binary adders generate an output signal that is received by the first shift register. The signal propagates through all the shift registers to the last shift register. The last shift register outputs a pseudo-random sequence.

A pseudo-random sequence generator for use within a universal lidar system and its corresponding method of operation. The pseudo-random sequence generator uses synchronized shift registers that are in series Binary adders are provided. The signal output of each of the shift registers is tapped and directed to the binary adders. High-speed switches are provided between the shift registers and the binary adders. The switches are programmed to connect only two of the shift registers to the binary adders for each of the pseudo-random patterns being generated. The binary adders generate an output signal that is received by the first shift register. The signal propagates through all the shift registers to the last shift register. The last shift register outputs a pseudo-random sequence.

A spread spectrum switching power converter circuit includes: a power stage circuit which includes an inductor and a power switch and is configured to switch the power switch according to a switching signal having spread spectrum for power conversion; a variable frequency oscillator, which generates a spread spectrum clock signal according to a spread spectrum control signal; a spread spectrum control circuit, which generates the spread spectrum control signal according to a first clock signal and a second clock signal; and a pulse width modulation circuit, configured to generate the switching signal according to a feedback signal based on the spread spectrum clock signal. The spread spectrum control circuit generates the spread spectrum control signal by sampling and combining a periodic waveform and a random waveform. The random waveform is generated according to the first clock signal and the periodic waveform is generated according to the second clock signal.

A memory device that includes a memory array and a memory controller is introduced. The memory controller is configured to adjust a program strength of the program pulse according to the configurable ratio of the first bit value and the second bit value to generate an adjusted program pulse or to adjust a bias voltage pair according to the configurable ratio of the first bit value and the second bit value to generate an adjusted bias voltage pair. The memory controller is further configured to generate the random bit stream with the configurable ratio of the first bit value and the second bit value according to the data stored in the plurality of memory cells included in the memory array after applying the adjusted program pulse or according to the data stored in the plurality of memory cells after being biased by the adjusted bias voltage pair.

A memory device that includes a memory array and a memory controller is introduced. The memory controller is configured to adjust a program strength of the program pulse according to the configurable ratio of the first bit value and the second bit value to generate an adjusted program pulse or to adjust a bias voltage pair according to the configurable ratio of the first bit value and the second bit value to generate an adjusted bias voltage pair. The memory controller is further configured to generate the random bit stream with the configurable ratio of the first bit value and the second bit value according to the data stored in the plurality of memory cells included in the memory array after applying the adjusted program pulse or according to the data stored in the plurality of memory cells after being biased by the adjusted bias voltage pair.

A noise reduction circuit for a matrix LED driver includes a pseudo random number generator, an up counter, a clock module, and a plurality of matrix switch controllers. The matrix switch controllers and the up counter randomly change a power-on sequence applied across matrix switches in the matrix LED driver according to working random numbers generated by the pseudo random number generator. The circuit prevents jitter-induced noise from periodically reoccurring at the power source of the matrix LED driver, thereby reducing noise energy.

A noise reduction circuit for a matrix LED driver includes a pseudo random number generator, an up counter, a clock module, and a plurality of matrix switch controllers. The matrix switch controllers and the up counter randomly change a power-on sequence applied across matrix switches in the matrix LED driver according to working random numbers generated by the pseudo random number generator. The circuit prevents jitter-induced noise from periodically reoccurring at the power source of the matrix LED driver, thereby reducing noise energy.