A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal.

A photonic circuit for generating an ultrafast clock for a photonic processor. The photonic circuit includes a beam splitter, a phase shifter, a first photonic combiner coupled to the beam splitter and the phase shifter, and a second photonic combiner coupled to the beam splitter and the first photonic combiner. The beam splitter splits a received photonic seed clock signal into a first photonic seed clock signal and a second photonic seed clock signal. The phase shifter shifts a phase of a received photonic signal to generate a phase-shifted version of the photonic signal. The first photonic combiner combines the second photonic seed clock signal with the phase-shifted version of the photonic signal to generate a first combined photonic signal. The second photonic combiner combines a delayed and attenuated version of the first photonic seed clock signal with the first combined photonic signal to generate a photonic clock signal.

A photonic circuit for generating an ultrafast clock for a photonic processor. The photonic circuit includes a beam splitter, a phase shifter, a first photonic combiner coupled to the beam splitter and the phase shifter, and a second photonic combiner coupled to the beam splitter and the first photonic combiner. The beam splitter splits a received photonic seed clock signal into a first photonic seed clock signal and a second photonic seed clock signal. The phase shifter shifts a phase of a received photonic signal to generate a phase-shifted version of the photonic signal. The first photonic combiner combines the second photonic seed clock signal with the phase-shifted version of the photonic signal to generate a first combined photonic signal. The second photonic combiner combines a delayed and attenuated version of the first photonic seed clock signal with the first combined photonic signal to generate a photonic clock signal.

Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.

Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.

A method for generating gigahertz bursts of laser pulses is provided, where: 1) time delay T2 of the delayed part with respect to the undelayed part of the input pulse is longer than a time period T1 between said input pulse and the next input pulse; 2) the bursts of output pulses have an incrementally increasing number of pulses; 3) intra-burst pulse separation inside the formed bursts is equal to T3=T2T1 and corresponds to an ultra-high pulse repetition rate higher than 100 MHz. In another embodiment: 1) T2 is longer than M*T1, where M=2, 3, etc.; 2) output train of bursts is composed of bursts of pulses wherein M adjacent bursts have identical number of pulses; 3) T3 is equal to T3=T2M*T1. The laser apparatus for implementing the method is provided.

An embodiment of a timing-based signal valley detection technique improves efficiency and reduces electromagnetic emissions due to ringing by controlling the off-time of a power switch in an LED driver or power converter application. The timing-based technique estimates a time of occurrence of a valley in the drain voltage of the power switch. The timing-based technique uses an analog comparator to sense the drain voltage of a power switch. The timing-based technique uses digital circuits to estimate the time of occurrence of the valley in the drain voltage and to adjust the duty cycle (e.g., adjusts the off-time by terminating the off-time) of a gate control signal of the power switch. The technique may use off-chip resistive voltage divider circuits to sense the drain voltage of the power switch and to generate a reference voltage and other circuits are integrated in an integrated circuit device.

An embodiment of a timing-based signal valley detection technique improves efficiency and reduces electromagnetic emissions due to ringing by controlling the off-time of a power switch in an LED driver or power converter application. The timing-based technique estimates a time of occurrence of a valley in the drain voltage of the power switch. The timing-based technique uses an analog comparator to sense the drain voltage of a power switch. The timing-based technique uses digital circuits to estimate the time of occurrence of the valley in the drain voltage and to adjust the duty cycle (e.g., adjusts the off-time by terminating the off-time) of a gate control signal of the power switch. The technique may use off-chip resistive voltage divider circuits to sense the drain voltage of the power switch and to generate a reference voltage and other circuits are integrated in an integrated circuit device.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.